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M2228 	Video
M2301 	Video
M2302 	Video
M2308 	Video
M2401 	Video
M3125 	Video
M3135 	Video (super VGA)
M3143 	Video
M3145 	PCI Video
M3145 	VLB/PCI 3D Video
M3147V 	PCI Video
M3149 	Video
M3151 	PCI 3D Video, 4MB MAX
M3307   MPEG    Video Decoder Chip
M3309   MPEG-II Video Decoder Chip
M3321   MPEG-II A/V Decoder Chip
M3351   MPEG-II Video Decoder Chip
M4803 	PCI EIDE Controller
M5105 	VLB Super I/O Controller FDD/HDD/LPT/2xCOM/GAME	 
M5113   Superset of 5105, with PnP, ECP/EPP LPT and IR port
M5119 	Super I/O
M5123 	Super I/O   PnP/2xCOM/IR port/Keyboard (For Phoenix BIOS)
M5125 	same as  M5123 but for AMI
M513? 	Super I/O PnP/Keyboard
M5135F 	Super I/O PnP/Keyboard/IR
M514? 	Super I/O PnP/Keyboard/IR/2xCOM/  
M5213 	PCI IDE
M5217/H	Super I/O
M5219 	PCI? Bus mastering EIDE
M5225 	PCI? EIDE
M5229 	PCI? Bus mastering EIDE
M5235 	Super I/O
M5237 	PCI USB Host
M5240 	PCI? EIDE
M5241 	PCMCIA Bridge
M5242 	? 
M5244 	FDD
M5427 	PCI-AGP Bridge
M5451 	Audio 
M5453 	Modem 
M5455 	Audio  

*AMD . . . . . . . [no datasheets, some info]...
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**82495XP/490XP Cache Controller / Cache RAM (for i860)       06/05/91
***Notes:...
***Info:...
***Features:...
**82496/491     Cache Controller / Cache RAM (for P5 Pentium) 03/22/93...
**82497/492   Cache Controller / Cache RAM (for P54 Pentium)    <Nov94...
**82498/493   Cache Controller / Cache RAM (for P54 Pentium)    <Nov94...
**
**Later chipsets (basic spec):
**440 series:...
**450NX  (?)            06/29/98:...
**?????  (Profusion)    c:99...
**800 series...
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*TI (Texas Instruments)...
**SN74LS610/2 IBM AT: SN74LS610, SN74LS612 Memory Mappers          <84
***Notes:...
***Info:
Each 'LS610  and 'LS612  memory mapper  integrated circuit  contains a
4-line to  16-line decoder, a  16-word by  12-bit RAM, 16  channels of
2-line to 1-line multiplexers, and  other miscellaneous circuitry on a
monolithic chip. Each  'LS610 also contains 12 latches  with an enable
control.

The memory  mappers are designed  to expand a  microprocessor's memory
addressing capability by  eight bits. Four bits of  the memory address
bus (see  System Block Diagram)[see  datasheet] can be used  to select
one of 16 map registers that contain  12 bits each.  these 12 bits are
presented  to the  system memory  address bus  through the  map output
buffers  along with  the  unused  memory address  bits  from the  CPU.
However, addressable memory space  without reloading the map registers
is the  same as would  be available with  the memory mapper  left out.
The  addressable  memory  space  is  increased  only  by  periodically
reloading the  map registers  from the  data bus.   This configuration
lends itself  to memory utilization  of 16 pages of  2^(n-4) registers
each  without reloading  (n -  number of  address bits  available from
CPU).

These  devices have  four modes  of operation:  read, write,  map, and
pass.  Data may be read from  or loaded into the map register selected
by  the register select  inputs (RS0  thru RS3)  under control  of R/W
whenever chip select (CS) is low. The data I/O takes place on the data
bus DO thru D7. The map  operation will output the contents of the map
register selected by the map address  inputs (MA0 thru MA3) when CS is
high and  MM (map mode control)  is low. The 'LS612  output stages are
transparent in this mode, while  the 'LS610 outputs may be transparent
or latched. When CS and MM are both high (pass mode), the address bits
on MA0 thru MA3 appear at M08-MO11, respectively (assuming appropriate
latch control) with  low levels in the other bit  positions on the map
outputs.
***Versions:...
***Features:...
**TACT82000   3-Chip 286 [no datasheet]                            c89...
**TACT82411   Snake  Single-Chip AT Controller                     c90...
**TACT82S411  Snake+ Single-Chip AT Controller [no datasheet]      c91...
**TACT83000   AT 'Tiger' Chip Set (386)                            c89...
**TACT84500   AT Chip Set (486, EISA) [no datasheet, some info]    c91...
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