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M2228 	Video
M2301 	Video
M2302 	Video
M2308 	Video
M2401 	Video
M3125 	Video
M3135 	Video (super VGA)
M3143 	Video
M3145 	PCI Video
M3145 	VLB/PCI 3D Video
M3147V 	PCI Video
M3149 	Video
M3151 	PCI 3D Video, 4MB MAX
M3307   MPEG    Video Decoder Chip
M3309   MPEG-II Video Decoder Chip
M3321   MPEG-II A/V Decoder Chip
M3351   MPEG-II Video Decoder Chip
M4803 	PCI EIDE Controller
M5105 	VLB Super I/O Controller FDD/HDD/LPT/2xCOM/GAME	 
M5113   Superset of 5105, with PnP, ECP/EPP LPT and IR port
M5119 	Super I/O
M5123 	Super I/O   PnP/2xCOM/IR port/Keyboard (For Phoenix BIOS)
M5125 	same as  M5123 but for AMI
M513? 	Super I/O PnP/Keyboard
M5135F 	Super I/O PnP/Keyboard/IR
M514? 	Super I/O PnP/Keyboard/IR/2xCOM/  
M5213 	PCI IDE
M5217/H	Super I/O
M5219 	PCI? Bus mastering EIDE
M5225 	PCI? EIDE
M5229 	PCI? Bus mastering EIDE
M5235 	Super I/O
M5237 	PCI USB Host
M5240 	PCI? EIDE
M5241 	PCMCIA Bridge
M5242 	? 
M5244 	FDD
M5427 	PCI-AGP Bridge
M5451 	Audio 
M5453 	Modem 
M5455 	Audio  

*AMD . . . . . . . [no datasheets, some info]...
*Chips & Technologies...
*Contaq  . . . . . [no datasheets, some info]...
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**82498/493   Cache Controller / Cache RAM (for P54 Pentium)    <Nov94
***Notes:...
***Info:
The 82498 Cache Controller and multiple 82493 Cache SRAMs combine with
the Pentium processor (735/90,  815/100) and future Pentium Processors
to form a CPU Cache chip set designed for high performance servers and
function-rich  desktops. The high-speed  interconnect between  the CPU
and  cache components has  been optimized  to provide  zero-wait state
operation. This CPU  Cache chip set is fully  compatible with existing
software,  and has new  data integrity  features for  mission critical
applications.

The 82498 Cache Controller implements the MESI write-back protocol for
full multiprocessing support.  Dual ported buffers and registers allow
the 82498  to concurrently  handle CPU bus,  memory bus,  and internal
cache operation for maximum performance.

The 82493 is a customized high-performance SRAM that supports 64-, and
128-bit  wide memory  bus widths,  32-,  and 64-byte  line sizes,  and
optional sectoring. The  data path between the CPU  bus and memory bus
is  separated  by  the  82493,  allowing  the  CPU  bus  to  handshake
synchronously,  asynchronously,  or   with  a  strobed  protocol,  and
allowing concurrent CPU bus and memory bus operations.

***Configurations:...
***Features:...
**
**Later chipsets (basic spec):
**440 series:
***440FX (Natoma)       05/06/96...
***440LX (Balboa)       08/27/97...
***440BX (Seattle)      c:Apr'98...
***440DX (?)            c:?...
***440EX (?)            c:Apr'98...
***440GX (Marlinespike) 06/29/98...
***440ZX & 440ZX-66 (?) 01/04/99...
***440ZX-M (?)          05/17/99...
***440MX (Banister)     05/17/99...
**450NX  (?)            06/29/98:...
**?????  (Profusion)    c:99...
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