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**82495DX/490DX DX CPU-Cache Chip Set <Sep91
***Notes:...
***Info:...
***Configurations:...
***Features:
o 50 MHz Intel486 DX CPU
- RISC Integer Core with Frequent Instructions Executing in One
Clock
- 160 Mbyte/Sec Burst Bus
- 41 Dhrystone MIPs
- 11.5M Double Precision Whetstones/Sec.
- On-Chip Cache and FPU
o Highly Flexible
- Supports 128 Kbyte and 256 Kbyte Configurations
- Complete MESI Protocol Support
- 32- or 64-Bit Memory Bus Width
- Synchronous, Asynchronous, and Strobed Memory Bus Protocols
- Variable Cache Line Sizes and Sectoring
- Cache Data Parity Option
o High Performance Second Level Cache
- Two-Way Set Associative
- Write-Back or Write Through Cache
- Zero Wait State Cache Access
- Concurrent CPU Bus, Memory Bus, and Internal Array Operation
o Full Multiprocessing Support
- Implements MESI Write-Back Cache Protocol
- Low Bus Utilization
- Automatically Maintains 1st Level Cache Consistency
- Supports Read-for-Ownership, Write-Allocation, and Cache-to-
Cache Transfers
**82495XP/490XP Cache Controller / Cache RAM (for i860) 06/05/91...
**82496/491 Cache Controller / Cache RAM (for P5 Pentium) 03/22/93...
**82497/492 Cache Controller / Cache RAM (for P54 Pentium) <Nov94...
**82498/493 Cache Controller / Cache RAM (for P54 Pentium) <Nov94...
**
**Later chipsets (basic spec):
**440 series:...
**450NX (?) 06/29/98:...
**????? (Profusion) c:99...
**800 series...
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*TI (Texas Instruments)...
**SN74LS610/2 IBM AT: SN74LS610, SN74LS612 Memory Mappers <84
***Notes:...
***Info:...
***Versions:...
***Features:...
**TACT82000 3-Chip 286 [no datasheet] c89...
**TACT82411 Snake Single-Chip AT Controller c90...
**TACT82S411 Snake+ Single-Chip AT Controller [no datasheet] c91...
**TACT83000 AT 'Tiger' Chip Set (386) c89...
**TACT84500 AT Chip Set (486, EISA) [no datasheet, some info] c91...
**Other:...
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**Other:
***VLX*XXX...
***VL16XXX...
***VL65XXX...
***VL80XXX...
***VL82XXX...
***VL85XXX...
***VL86XXX...
***VXXXXXX...
**Not sure if they actually exist...
*Western Digital...
*Winbond...
*ZyMOS...
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