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**82497/492 Cache Controller / Cache RAM (for P54 Pentium) <Nov94
***Notes:...
***Info:
The 82497 Cache Controller and multiple 82492 Cache SRAMs combine with
the Pentium processor (735\90, 810\100) to form a CPU Cache chip set
designed for high performance servers and function-rich desktops. The
high-speed interconnect between the CPU and cache components has been
optimized to provide zero-wait state operation. This CPU Cache chip
set is fully compatible with existing software, and has new data
integrity features for mission critical applications.
The 82497 cache controller implements the MESI write-back protocol for
full multiprocessing support. Dual ported buffers and registers allow
the 82497 to concurrently handle CPU bus, memory bus, and internal
cache operation for maximum performance.
The 82492 is a customized high-performance SRAM that supports 32-,
64-, 128-bit wide memory bus widths, 16-, 32-, and 64-byte line sizes,
and optional sectoring. The data path between the CPU bus and memory
bus is separated by the 82492, allowing the CPU bus to handshake
synchronously, asynchronously, or with a strobed protocol, and
allowing concurrent CPU bus and memory bus operations.
***Configurations:...
***Features:...
**82498/493 Cache Controller / Cache RAM (for P54 Pentium) <Nov94...
**
**Later chipsets (basic spec):
**440 series:...
**450NX (?) 06/29/98:...
**????? (Profusion) c:99...
**800 series...
*Headland/G2...
*HMC (Hulon Microelectronics)...
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*Motorola...
*OPTi...
**82c465MV/A/B Single-Chip Mixed Voltage Notebook Solution <Oct97
***Info:...
***Configurations:...
***Features:...
**82C481?/482? HiP/486 & HiB/486 [no datasheet] Oct89...
**82C491/392 486WB PC/AT Chipset <04/21/91...
**82C493/392 486SXWB <10/21/91...
**82C495SX/392SX LCWB PC/AT chipset [no datasheet] ?...
**82C495SLC DXSLC 386/486 Low Cost Write Back c:92...
**82C495XLC PC/AT Chip Set c:93...
**82c496A/B DXBB PC/AT Chipset <Mar92...
**82C496/7 DXBB PC/AT Chipset (Cached) <01/16/92...
**82C498 DXWB PC/AT chipset [no datasheet] ?...
**82C499 DXSC DX System Controller c:93...
**82C546/547 Python PTM3V c:94...
**82C556/7/8 Viper [no datasheet] ?...
**82C556/7/8N Viper-N Viper Notebook Chipset <05/25/95...
**82C556M/7M/8E Viper-N+ Viper Notebook Chipset c:96...
**82C566/7/8 Viper-Max Chipset Scalable MultiMedia PC Solution ?...
**82C571/572 486/Pentium c:93...
**82C576/7/8 Viper Xpress [no datasheet] ?...
**82C576/8/9 Viper XPress+ [no datasheet, some info] <01/16/97...
**82C596/597 PTMAWB Pentium Adaptive Write-back (Cobra) c:93...
**82C650/1/2 Discovery (Pentium Pro) [no datasheet] ?...
**82C681/2/6/7 386/486WB EISA c:92...
**82C683 386/486AWB EISA [no datasheet] ?...
**82C693/6/7 Pentium uP Write Back Cache EISA c:93...
**82C700 FireStar c:97...
**82C701 FireStar Plus c:97...
**82C750 Vendetta [no datasheet] ?...
**82c801 SCWB2 DX Single Chip Solution c:92...
**82C802 SCWB2 PC/AT Single Chip [no datasheet] ?...
**82C802G/GP System/Power Management Controller (cached) c:93...
**82C895 System/Power Management Controller (cached) c:Sep94...
**82C898 System/Power Management Controller (non-cache)c:Nov94...
**
**Support Chips:
**82C601/2 Buffer Devices <Nov94...
**82C822 PCIB (VLB-to-PCI bridge) c:94...
**Other:...
*PC CHIPS/Amptron/Atrend/ECS/Elpina/etc...
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*Unresearched:...
*VIA...
*VLSI...
**VL82C110 Combination I/O chip ?
***Info:
The VL82C110 Combination I/O chip replaces several of the commonly
used peripherals found in PC/AT-compatible computers. The VL82C110
contains a 765A compatible floppy disk controller with a digital data
clock separator, writ precompensation logic and the necessary control
registers. It also contains two 16C450 compatible UARTs, a Centronics
compatible printer port, and an internal PMU (power management unit)
which is useful in applications where low power consumption is
essential. Additionally, a PLL clock circuit is included to provide
one of seven of the commonly used CPU clock frequencies. This 100-pin
chip allows designers to implement a very cost-effective, minimum chip
count motherboard containing functions that are common to virtually
all PCs.
The internal PMU provides a Sleep output which OS asserted via
automatically after a programmable time delay period of inactivity in
any of the major on-chip functions. Conversely, the sleep output will
be de-asserted when any activity is detected to any of the major
on-chip functions.
The on-chip UARTs are 100% software compatible with the VL16C450 ACE.
The bidirectional parallel port provides a PS/2 software compatible
interface between a Centronics-style printer and the VL82C110. Direct
drive is provided so that all that is necessary to interface to the
line printer is a resistor-capacitor network. The bidirectional
feature (option) is software programmable for backwards PC/AT-
compatibility.
The on-chip disk controller OS 100% compatible to the industry
standard 765A. The internal digital data separator is capable of
operating up to a 500 kb/s data rate. The Controller also implements
all of the DP8473 disk controller functions.
The necessary signals are provided to implement the Integrated Drive
Electronics (IDE) interface.
A 24 MHz oscillator is included for UART baud rate generation and the
floppy disk controller clock, It is also used to generate, via
software control, a 20, 25, 32, 40, 50, 66 or 80 MHz output which can
be used as a CPU input clock. This feature may be disabled at power-up
reset time.
Software configurable registers are provided to enable and disable
major blocks, assign addresses, and control other functions within the
VL82C110.
***Versions:...
***Features:...
**VL82C113 SCAMP Combination I/O chip ?...
**VL82C114 Combination I/O chip ?...
**Video: ...
**Disk:...
**Modems:...
**Other:...
**Not sure if they actually exist...
*Western Digital...
*Winbond...
*ZyMOS...
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