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**440 series:
***440FX (Natoma) 05/06/96...
***440LX (Balboa) 08/27/97...
***440BX (Seattle) c:Apr'98...
***440DX (?) c:?...
***440EX (?) c:Apr'98
Chips:
[82443EX] (PAC) [82371AB/EB] (PIIX4/4E)
CPUs: Single P-II/Celeron
DRAM Types: EDO SDRAM
Mem Rows: 4
DRAM Density: 16Mbit 64Mbit
Max Mem: 256MB
ECC/Parity: No
AGP speed: 1x 2x
Bus Speed: 66
PCI Clock/Bus: 1/2 PCI 2.1
***440GX (Marlinespike) 06/29/98...
***440ZX & 440ZX-66 (?) 01/04/99...
***440ZX-M (?) 05/17/99...
***440MX (Banister) 05/17/99...
**450NX (?) 06/29/98:...
**????? (Profusion) c:99...
**800 series...
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*PC CHIPS/Amptron/Atrend/ECS/Elpina/etc...
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*TI (Texas Instruments)...
**TACT83000 AT 'Tiger' Chip Set (386) c89
***Info:...
***Configurations:...
***Features:
o High-Speed 1-um CMOS Technology Supports System Speeds up to
33 MHz
o Fully AT-Compatible 386 Three-Chip SX, Four-Chip DX Solutions
o Only Four Additional Logic Chips Needed
o Major Features Programmable Through Software
o TACT83442 Memory Control Unit (MCU)
- Cascadable up to Eight Devices
- Address Range of up to 32M Byte Per Device, 256M Byte Fully
Cascaded
- Supports 256K-, 1M-, and 4M-Bit DRAMs in Normal, Page, Word-
interleave, and Page Block-interleave Modes
- Programmable DRAM Timing Parameters
- Supports up to Two Memory Banks for 32-Bit Systems and Four
Banks for 16-Bit Systems
- Can Directly Drive up to 36 DRAM Devices
- Shadow RAM Available Between 0C 0000h and 0F FFFFh
- Contains Global Page Mapping RAM Allowing Remap of
- 64K-Byte Memory Blocks Above 1M Byte
- 16K-Byte Memory Blocks Below 1M Byte
o TACT83443 AT Bus Interface Unit (ATU)
- Internal Clock Switching Between Two Independent Frequencies
Controlled by Software
- Asynchronous AT Bus Interface With Write Buffer Option
- Full AT Direct-Drive Capability
- Extended Direct Memory Access Mode for 32-Bit Operation
- Fast CPU Reset and A20 GATE Modification
- Numeric Processor Interface for 387SX, 387DX, and Weitek 3167
- Integrates All Essential AT Peripherals
- Real Time Clock With 128-Byte CMOS RAM
o TACT83441 Data Path Unit (DPU)
- 8- and 16-Bit Data Bus Sizing
- Data Path Cascadable to 32 Bits
- Write Buffer Capability for AT Bus Access
- Supports Posted Write Operations From Cache Controller
- Parity Generation and Checking Logic
**TACT84500 AT Chip Set (486, EISA) [no datasheet, some info] c91...
**Other:...
*UMC...
*Unresearched:...
*VIA...
*VLSI...
**VL82C107 SCAMP Combination I/O chip ?
***Info:...
***Versions:...
***Features:...
**VL82C108 TOPCAT Combination I/O chip ?...
**VL82C110 Combination I/O chip ?...
**VL82C113 SCAMP Combination I/O chip ?...
**VL82C114 Combination I/O chip ?...
**Video: ...
**Disk:...
**Modems:...
**Other:...
**Not sure if they actually exist...
*Western Digital...
*Winbond...
*ZyMOS...
*General Sources:...
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