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**82495XP/490XP Cache Controller / Cache RAM (for i860) 06/05/91
***Notes:...
***Info:...
***Features:...
**82496/491 Cache Controller / Cache RAM (for P5 Pentium) 03/22/93...
**82497/492 Cache Controller / Cache RAM (for P54 Pentium) <Nov94...
**82498/493 Cache Controller / Cache RAM (for P54 Pentium) <Nov94...
**
**Later chipsets (basic spec):
**440 series:...
**450NX (?) 06/29/98:...
**????? (Profusion) c:99...
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*TI (Texas Instruments)...
**SN74LS610/2 IBM AT: SN74LS610, SN74LS612 Memory Mappers <84
***Notes:...
***Info:
Each 'LS610 and 'LS612 memory mapper integrated circuit contains a
4-line to 16-line decoder, a 16-word by 12-bit RAM, 16 channels of
2-line to 1-line multiplexers, and other miscellaneous circuitry on a
monolithic chip. Each 'LS610 also contains 12 latches with an enable
control.
The memory mappers are designed to expand a microprocessor's memory
addressing capability by eight bits. Four bits of the memory address
bus (see System Block Diagram)[see datasheet] can be used to select
one of 16 map registers that contain 12 bits each. these 12 bits are
presented to the system memory address bus through the map output
buffers along with the unused memory address bits from the CPU.
However, addressable memory space without reloading the map registers
is the same as would be available with the memory mapper left out.
The addressable memory space is increased only by periodically
reloading the map registers from the data bus. This configuration
lends itself to memory utilization of 16 pages of 2^(n-4) registers
each without reloading (n - number of address bits available from
CPU).
These devices have four modes of operation: read, write, map, and
pass. Data may be read from or loaded into the map register selected
by the register select inputs (RS0 thru RS3) under control of R/W
whenever chip select (CS) is low. The data I/O takes place on the data
bus DO thru D7. The map operation will output the contents of the map
register selected by the map address inputs (MA0 thru MA3) when CS is
high and MM (map mode control) is low. The 'LS612 output stages are
transparent in this mode, while the 'LS610 outputs may be transparent
or latched. When CS and MM are both high (pass mode), the address bits
on MA0 thru MA3 appear at M08-MO11, respectively (assuming appropriate
latch control) with low levels in the other bit positions on the map
outputs.
***Versions:...
***Features:...
**TACT82000 3-Chip 286 [no datasheet] c89...
**TACT82411 Snake Single-Chip AT Controller c90...
**TACT82S411 Snake+ Single-Chip AT Controller [no datasheet] c91...
**TACT83000 AT 'Tiger' Chip Set (386) c89...
**TACT84500 AT Chip Set (486, EISA) [no datasheet, some info] c91...
**Other:...
*UMC...
*Unresearched:...
*VIA...
*VLSI...
**VL82C521/522 Lynx/M ?
***Info:...
***Configurations:...
***Features:
o Support for Pentium and Pentium-class CPUs
o 64-bit wide SDRAM, EDO, and FPM DRAM controller
o Nine-deep, 64-bit fast-access smart write buffers
o Fully PCI 2.1 compliant, 33MHz, synchronous or asynchronous, high
performance (120 MB/s) PCI bus with full concurrency to support
high bandwidth multi-media
o Flexible L2 write-back cache controller supporting 3-1-1-1-1-1-1-1
burst cycles
o Highly integrated chipset in low-profile BGA packages
o Active thermal feedback (ATF) for closed-loop thermal control of
the CPU
o PCI bridge support for high-performance primary PCI hot docking
o Common Architecture Serial Bus minimizes docking connector pin
count
o SMB/I2C system management bus improves battery monitoring
o Singular ROM for keyboard, System and graphics BIOS
o Full 2 channel Bus Mastering IDE controller
o Integrated '077 FDC
o Two 16550 UARTs
o 8052 keyboard controller with built-in scan for matrix keyboards and
boot controller functionality
o system clocks from power-managed PLLs with on-board buffering for
distribution
o Two PWMs to provide LCD backlight and contrast control
o Parallel port with PS2, EPP and ECP extensions
o Built-in IrDA 1.1 Fast Infrared communications port
o Multiple VCC rails and on-board level shifters to provide inder-
pendent power-down and true 5.0 Vdc peripheral support
o Support for three PS2 ports
o Real-Time Clock with CMOS
o 25 GPIO pins with expansion
o Built-in Sub-ISA bus for 16-bit DMA ISA Master audio device
o Supports 3.3V and 0V suspend with multiple resume events, I/O
trapping, and audio 0V suspend/resume
o Bus Keeper I/Os to reduce battery drain in suspend mode
o Supports shut-down option for CPU core power during powered
suspend to maximize battery life
o Supports CPU clock division emulation to effectively reduce CPU
clock frequency
o Plug-N-Play support
o Compliant with Microsoft recommendations for Win '95
**VL82C530 Eagle Ð c95...
**VL82C541/543 Lynx c95...
**VL82C591/593 SuperCore 590 c94...
**VL82C594/596/597 Wildcat c95...
**I/O Chips:
**VL82C106 Combination I/O chip ?...
**VL82C107 SCAMP Combination I/O chip ?...
**VL82C108 TOPCAT Combination I/O chip ?...
**VL82C110 Combination I/O chip ?...
**VL82C113 SCAMP Combination I/O chip ?...
**VL82C114 Combination I/O chip ?...
**Video: ...
**Disk:...
**Modems:...
**Other:...
**Not sure if they actually exist...
*Western Digital...
*Winbond...
*ZyMOS...
*General Sources:...
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