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**82495DX/490DX DX CPU-Cache Chip Set <Sep91
***Notes:...
***Info:...
***Configurations:...
***Features:...
**82495XP/490XP Cache Controller / Cache RAM (for i860) 06/05/91...
**82496/491 Cache Controller / Cache RAM (for P5 Pentium) 03/22/93...
**82497/492 Cache Controller / Cache RAM (for P54 Pentium) <Nov94...
**82498/493 Cache Controller / Cache RAM (for P54 Pentium) <Nov94...
**
**Later chipsets (basic spec):
**440 series:...
**450NX (?) 06/29/98:...
**????? (Profusion) c:99...
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**82C566/7/8 Viper-Max Chipset Scalable MultiMedia PC Solution ?
***Info:...
***Configurations:...
***Features:...
**82C571/572 486/Pentium c:93...
**82C576/7/8 Viper Xpress [no datasheet] ?...
**82C576/8/9 Viper XPress+ [no datasheet, some info] <01/16/97...
**82C596/597 PTMAWB Pentium Adaptive Write-back (Cobra) c:93...
**82C650/1/2 Discovery (Pentium Pro) [no datasheet] ?...
**82C681/2/6/7 386/486WB EISA c:92...
**82C683 386/486AWB EISA [no datasheet] ?...
**82C693/6/7 Pentium uP Write Back Cache EISA c:93...
**82C700 FireStar c:97...
**82C701 FireStar Plus c:97...
**82C750 Vendetta [no datasheet] ?...
**82c801 SCWB2 DX Single Chip Solution c:92...
**82C802 SCWB2 PC/AT Single Chip [no datasheet] ?...
**82C802G/GP System/Power Management Controller (cached) c:93...
**82C895 System/Power Management Controller (cached) c:Sep94...
**82C898 System/Power Management Controller (non-cache)c:Nov94...
**
**Support Chips:
**82C601/2 Buffer Devices <Nov94...
**82C822 PCIB (VLB-to-PCI bridge) c:94...
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*PC CHIPS/Amptron/Atrend/ECS/Elpina/etc...
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*Unresearched:...
*VIA...
*VLSI...
**VL82C481 System/Cache/ISA bus Controller c92
***Basics:...
***Info:...
***differences to the VL82C480:
"It also supports 486 family CPUs that contain an integrated
write-back cache (P24T, etc.)"
"It can also perform 3-2-2-2 cycle reads for support of slower SRAMs
at higher frequences."
"The HITM# input is provided to force the VL82C481 to abort DRAM or
cache cycles when a hit on a dirty line in the CPU write-back cache is
detected. the DRAM or cache cycle is subsequently restarted after the
CPU has written back the dirty data"
"Further support for devices that reside on the local bus is provided
through use of the <*LDEV#*> (Local Bus Access) input, which deselects
the VL82C481 during CPU cycles <*and causes the VL82C481 to generate
VL-Bus memory cycles when active dur- ing DMA and Master Mode
cycles*>."
[areas marked <* *> are differences or additions, in the VL82C480
LDEV# is LBA#]
<*On power-on default,*> The chip does not generate parity for CPU
writes to DRAM, but does generate cache write-back cycles. <*However,
a mode is provided in which the VL82C481 will generate parity during
either CPU writes or VL master writes.*>
[areas marked <* *> are additions]
***Configurations:...
***Features:...
**VL82C486 Single-Chip 486, SC486, Controller ?...
**VL82C425 486 Cache controller ?...
**???????? Cheetah 486, PCI [no datasheet] ?...
**VL82C3216 Bus Expanding Controller Cache with write buffer ?...
**VL82C521/522 Lynx/M ?...
**VL82C530 Eagle Ð c95...
**VL82C541/543 Lynx c95...
**VL82C591/593 SuperCore 590 c94...
**VL82C594/596/597 Wildcat c95...
**I/O Chips:
**VL82C106 Combination I/O chip ?...
**VL82C107 SCAMP Combination I/O chip ?...
**VL82C108 TOPCAT Combination I/O chip ?...
**VL82C110 Combination I/O chip ?...
**VL82C113 SCAMP Combination I/O chip ?...
**VL82C114 Combination I/O chip ?...
**Video: ...
**Disk:...
**Modems:...
**Other:...
**Not sure if they actually exist...
*Western Digital...
*Winbond...
*ZyMOS...
*General Sources:...
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