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**M6117          386SX Single Chip PC                              <97
***Notes:...
***Info:...
***Versions:...
***Features:
o   Static Intel 386SX compatible Core 
    - Operating Power Supply  5.0V 
    - Operating frequency 25Mhz to 40Mhz 
o   Memory Controller
    - Supports EDO DRAM 
    - Supports on board memory size up to 16M bytes for 386SX or 64M 
      bytes upgrade system using 256K, 512K, 1M, 4M or 16M SIMMs 
    - Supports up to 4-bank DRAM interface 
    - Page interleave DRAM access for FP mode 
    - Programmable shadow RAM from A to B segment in 128K byte and C 
      to F segment in 32K byte unit 
    - Provides "RAS only" refresh or "CAS before RAS” refresh types 
    - Parity generation and checking 
o   Peripheral Interface 
    - Includes 2 cascaded 8237 DMA controllers 
    - Includes 1 74612 memory mapper 
    - Includes 2 cascaded 8259 interrupt controllers 
    - Includes 1 8254 programming counter 
o   ISA Interface
    - Executes cycles for requests from CPU, DMA and ISA bus master 
    - Assembles or de-assembles data for multiple bus cycle or 
      unmatched data width 
    - Generates refresh signals to ISA slots during DRAM refresh 
      cycles 
o   Built-in RTC 
    - Internal Real Time Clock that provides 128 byte CMOS RAM 
o   Programmable 2 channels chip select 
    - Provide chip select for memory  or I/O device without external 
      address decode random logic 
o   Built-In PS2/AT Keyboard Controller
    - Internal PS2/AT keyboard controller and mouse 
o   PMU interface 
    - Supports CPU SMM mode, SMI feature 
    - Supports APM control 
    - Provides External Suspend mode switch 
    - Provides four (4) system states for power saving (On, Doze, 
      Standby, Suspend) 
    - Supports RTC alarm wake up control 
o   Expandable GPI/O signals
    - Provides sixteen External power control input and output signals 
    - Provides sixteen independent pin for general purpose input and 
      output signals 
o   Watchdog timer 
    - When timer times out , a system reset or NMI or IRQ happens 
o   IDE interface
    - Provides a decoder for external IDE connection
o   Packaging 
    - 208-pin PQFP package

**
**Support Chips:
**M1535/D        South Bridge                                        ?...
**
**May not exist:...
**Later Chipsets:...
**Other:...
*AMD . . . . . . . [no datasheets, some info]...
*Chips & Technologies...
*Contaq  . . . . . [no datasheets, some info]...
*Efar Microsystems [no datasheets, some info]...
*ETEQ...
*Faraday...
*Forex . . . . . . [List only, no datasheets found]...
*Intel...
**82489DX       Advanced Programmable Interrupt Controller    10/12/92
***Notes:...
***Info:
1.0 INTRODUCTION

The  82489DX  Advanced   Programmable  Interrupt  Controller  provides
multiprocessor interrupt management, providing both static and dynamic
symmetrical interrupt distribution across all processors.

The main  function of the  82489DX is to provide  interrupt management
across all  processors. This  dynamic interrupt  distribution includes
routing of the interrupt to the lowest-priority processor. The 82489DX
works in  systems with multiple  I/O subsystems, where  each subsystem
can  have  its  own  set  of  interrupts.   This  chip  also  provides
inter-processor interrupts,  allowing any  processor to  interrupt any
processor or set  of processor. Each 82489DX I/O  init interrupt input
pin is individually  programmable by software as either  edge or level
triggered.  The interrupt vector and interrupt steering information an
be specified  per pin.  A  32-bit wide timer  is provided that  can be
programmed to interrupt the local processor.  the timer can be used as
a counter to provide a time base to software running on the processor,
or to generate  time slice interrupts locally to  that processor.  the
82489DX   provides   32-bit   software    access   to   its   internal
registers. Since no  82489DX register read have any  side effects, the
82489DX registers  can be aliased  to a  user read-only page  for fast
user access (e.g., performance monitoring timers).

The 82489DX  supports a generalized naming/addressing  scheme that can
be tailored by  software to fit a variety of  system architectures and
usage  models.   It  also  supports 8259A  compatibility  by  becoming
virtually  transparent with  regard to  an externally  connected 8259A
style controller, making the 8259A visible to software.

***Versions:...
***Features:...
**82495DX/490DX DX CPU-Cache Chip Set                           <Sep91...
**82495XP/490XP Cache Controller / Cache RAM (for i860)       06/05/91...
**82496/491     Cache Controller / Cache RAM (for P5 Pentium) 03/22/93...
**82497/492   Cache Controller / Cache RAM (for P54 Pentium)    <Nov94...
**82498/493   Cache Controller / Cache RAM (for P54 Pentium)    <Nov94...
**
**Later chipsets (basic spec):
**440 series:...
**450NX  (?)            06/29/98:...
**?????  (Profusion)    c:99...
**800 series...
*Headland/G2...
*HMC (Hulon Microelectronics)...
*Logicstar...
**Other:
SL7001 MDA Graphics Controller
SL5001 Parallel Printer Port Interface
SL2002 Dual Channel NRZI Encoder / Decoder
SL4000 Lan controller

*Motorola...
*OPTi...
*PC CHIPS/Amptron/Atrend/ECS/Elpina/etc...
*SIS...
*Symphony...
*TI (Texas Instruments)...
*UMC...
*Unresearched:...
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