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**82495DX/490DX DX CPU-Cache Chip Set <Sep91
***Notes:...
***Info:
The 50 MHz Intel486 DX CPU-Cache Chip Set provides a high performance
solution for servers and high-end desktop systems. This binary
compatible solution has been optimized to provide 50 MHz, zero wait
state performance. The CPU-Cache chip set combines the 50 MHz Intel486
Microprocessor with the 82495DX/82490DX cache subsystem. It delivers
integer performance of 41 V1.1 Dhrystone MlPs and a SPEC integer
rating of 27.9. The cache subsystem features the 82495DX Cache
Controller and the 82490DX Dual Ported Data RAM. Dual ported buffers
and registers of the 82490DX allow the 82495DX Cache Controller to
concurrently handle CPU bus, memory bus, and internal cache operations
for maximum performance.
The CPU-Cache Chip Set offers many features that are ideal for multi-
processor based systems. The Write-Back feature provides efficient
memory bus utilization by reducing bus traffic through eliminating
unnecessary writes to main memory. The CPU-Cache chip set also
supports MESI protocol and monitors the memory bus to guarantee cache
coherency.
The 50 MHz Intel486 DX CPU and 82495DX/82490DX Cache subsystem are
produced on Intel's latest CHMOS V process which features submicron
technology and triple layer metal.
3.0 ARCHITECTURAL OVERVIEW
3.1 Introduction
The Intel486 CPU-cache chip set provides a tightly coupled processing
engine based on the Intel486 microprocessor and a cache subsystem
comprised of the 82495DX cache controller and multiple 82490DX cache
components. Figure 3.1 [see datasheet] diagrams the basic config-
uration.
The cache subsystem provides a gateway between the CPU and the memory
bus. All CPU accesses that can be serviced locally are transparent to
the memory bus and serve to avoid bus traffic. As a result, the cache
chip set reduces memory bus bandwidth to both increase Intel486
processor performance and support efficient multiprocessor systems.
The cache subsystem also decouples the CPU from the memory bus to
provide zero-wait-state operation at high clock frequencies while
allowing relatively slow and inexpensive memories.
The CPU-cache chip set prevents latency and bandwidth bottlenecks
across a variety of uniprocessor and multiprocessor designs. The
processor’s on-chip cache supports a very wide CPU data bus and
high-speed data movement. The second-level cache greatly extends the
capabilities of the on-chip cache resources, enabling a larger portion
of memory cycles to be satisfied independently of the memory bus.
3.2 CPU-Cache Chip Set Description
The chip set is comprised of three functional blocks:
3.2.1 CPU
The chip set includes a special version of the Intel486DX micropro-
cessor at 50 MHz. The Intel486DX Microprocessor Data Sheet provides
complete component specifications.
3.2.2 CACHE CONTROLLER
The 82495DX cache controller is the main control element for the chip
set. providing tags and line states. and determining cache hits and
misses. The 82495DX executes all CPU bus requests and coordinates all
main memory accesses with the memory bus controller (MBC).
The 82495DX controls the data paths of the 82490DX cache components
for cache hits and misses and furnishes the CPU with needed data. The
controller dynamically adds wait states as needed using the most
recently used (MRU) prediction algorithm.
The 82495DX also performs memory bus snoop operations in shared memory
systems and drives the cycle address and other attributes during
memory bus accesses. Figure 3.2 [see datasheet] diagrams the 82495DX.
3.2.3 CACHE SRAM
Multiple 82490DX cache components provide the cache SRAM and data
path. Each component includes the latches, muxes and logic needed to
work in lock step with the 82495DX to efficiently serve both hit and
miss accesses. The 82490DX components take full advantage of VLSI
silicon flexibility to exceed the capabilities of discrete
implementations. The 82490DX components support zero-wait-state hit
accesses and concurrent CPU and memory bus accesses, and they
replicate MRU bits for autonomous way prediction. During memory bus
cycles. the 82490DX components act as a gateway between CPU and memory
buses. Figure 3.3 [see datasheet] diagrams an 82490DX cache component.
3.3 Secondary Cache Features
The 82495DX cache controller and 82490DX cache components provide a
unified, software transparent secondary data and instruction cache.
The cache enables a highspeed processor core that provides efficient
performance even when paired with a significantly slower memory bus.
The secondary cache interprets CPU bus cycles and can service most
memory read and write cycles without accessing main memory. I/O and
other special cycles are passed directly to the memory bus. The cache
has a dual-port structure that permits concurrent CPU and memory bus
operation.
The 82495DX cache controller contains the 8K tag entries and logic
needed to support a cache as large as 256K. Combinations of between 4
and 9 82490DX cache SRAMs are used to create caches ranging from 128K
to 256K, with or without data parity.
The MBC provides logic needed to interface the CPU, 82495DX and
82490DX to the memory bus. Because the MBC also affects system
performance. its design can be the basis of product differentiation.
***Configurations:...
***Features:...
**82495XP/490XP Cache Controller / Cache RAM (for i860) 06/05/91
***Notes:...
***Info:...
***Features:...
**82496/491 Cache Controller / Cache RAM (for P5 Pentium) 03/22/93...
**82497/492 Cache Controller / Cache RAM (for P54 Pentium) <Nov94...
**82498/493 Cache Controller / Cache RAM (for P54 Pentium) <Nov94...
**
**Later chipsets (basic spec):
**440 series:...
**450NX (?) 06/29/98:...
**????? (Profusion) c:99...
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*VIA...
**VT82C596/A Mobile PCI Integrated Peripheral Controller <11/05/97
***Info:...
***Versions:...
***Features:
o Inter-operable with VIA and other Host-to-PCI Bridges
- Combine with VT82C597 for a complete 66MHz Socket-7 PCI / AGP /
ISA system (Apollo VP3)
- Combine with VT82C598 for a complete 66 / 75 / 83 / 100MHz
Socket-7 PCI / AGP / ISA system (Apollo MVP3)
- Combine with VT82C691 for a complete Socket-8 or Slot-1 PCI /
ISA system (Apollo Pro)
- Inter-operable with Intel or other Host-to-PCI bridges for a
complete PC97 compliant PCI / AGP / ISA system
o Pin-compatible upgrade for PIIX4 for existing designs
o PC98 Compliant PCI to ISA Bridge
- Integrated ISA Bus Controller with integrated DMA, timer, and
interrupt controller
- Integrated Keyboard Controller with PS2 mouse support
- Integrated DS12885-style Real Time Clock with extended 256 byte
CMOS RAM and Day/Month Alarm for ACPI
- Integrated USB Controller with root hub and two function ports
- Integrated UltraDMA-33 master mode EIDE controller with enhanced
PCI bus commands
- PCI-2.1 compliant with delay transaction
- Eight double-word line buffer between PCI and ISA bus
- One level of PCI to ISA post-write buffer
- Supports type F DMA transfers
- Distributed DMA support for ISA legacy DMA across the PCI bus
- Sideband signal support for PC/PCI and serial interrupt for
docking and non-docking applications
- Fast reset and Gate A20 operation
- Edge trigger or level sensitive interrupt
- Flash EPROM, 2Mb EPROM and combined BIOS support
- Supports positive and subtractive decoding
- Supports external APIC interface for symmetrical multiprocessor
configurations
o UltraDMA-33 Master Mode PCI EIDE Controller
- Dual channel master mode PCI supporting four Enhanced IDE
devices
- Transfer rate up to 33MB/sec to cover PIO mode 4, multi-word DMA
mode 2 drives, and UltraDMA-33 interface
- Thirty-two levels (doublewords) of prefetch and write buffers
- Dual DMA engine for concurrent dual channel operation
- Bus master programming interface for SFF-8038i rev.1.0 and
Windows-95 compliant
- Full scatter gather capability
- Support ATAPI compliant devices including DVD devices
- Support PCI native and ATA compatibility modes
- Complete software driver support
- Supports glue-less “Swap-Bay” option with full electrical
isolation
o Universal Serial Bus Controller
- USB v.1.0 and Intel Universal HCI v.1.1 compatible
- Eighteen level (doublewords) data FIFO with full scatter and
gather capability
- Root hub and two function ports
- Integrated physical layer transceivers with over-current
detection status on USB inputs
- Legacy keyboard and PS/2 mouse support
o System Management Bus Interface
- Host interface for processor communications
- Slave interface for external SMBus masters
o Sophisticated PC97-Compatible Mobile Power Management
- Supports both ACPI (Advanced Configuration and Power Interface)
and legacy (APM) power management
- ACPI v1.0 Compliant
- APM v1.2 Compliant
- CPU clock throttling and clock stop control for complete ACPI C0
to C3 state support
- PCI bus clock run and PCI/CPU clock generator stop control
- Supports multiple system suspend types: power-on suspends with
flexible CPU/PCI bus reset options, suspend to DRAM, and suspend
to disk (soft-off), all with hardware automatic wake-up
- Multiple suspend power plane controls and suspend status
indicators
- One idle timer, one peripheral timer and one general purpose
timer, plus 24/32-bit ACPI compliant timer
- Normal, doze, sleep, suspend and conserve modes
- Global and local device power control
- System event monitoring with two event classes
- Primary and secondary interrupt differentiation for individual
channels
- Dedicated input pins for power and sleep buttons, external modem
ring indicator, and notebook lid open/close for system wake-up
- Up to 22 general purpose input ports and 31 output ports
- Multiple internal and external SMI sources for flexible power
management models
- Two programmable chip selects and one microcontroller chip
select
- Enhanced integrated real time clock (RTC) with date alarm, month
alarm, and century field
- Thermal alarm support
- Cache SRAM power-down control
- Hot docking support
- I/O pad leakage control
o Plug and Play Controller
- PCI interrupts steerable to any interrupt channel
- Three steerable interrupt channels for on-board plug and play
devices
- Microsoft Windows 95TM and plug and play BIOS compliant
o Built-in NAND-tree pin scan test capability
o 0.5u, 3.3V, low power CMOS process
o Single chip 324 pin BGA
**VT82C686A/B PCI Super-I/O Integrated Peripheral Ctrl. <02/10/98...
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