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**82485 Turbo Cache (and 485Turbocache) c90
***Notes:...
***Info:...
***Versions:...
***Features:...
**82489DX Advanced Programmable Interrupt Controller 10/12/92...
**82495DX/490DX DX CPU-Cache Chip Set <Sep91...
**82495XP/490XP Cache Controller / Cache RAM (for i860) 06/05/91...
**82496/491 Cache Controller / Cache RAM (for P5 Pentium) 03/22/93...
**82497/492 Cache Controller / Cache RAM (for P54 Pentium) <Nov94...
**82498/493 Cache Controller / Cache RAM (for P54 Pentium) <Nov94...
**
**Later chipsets (basic spec):
**440 series:...
**450NX (?) 06/29/98:...
**????? (Profusion) c:99...
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**Later Chipsets:
Info sourced from the very useful plasma-online.de:
http://www.plasma-online.de/index.html?content=http%3A//www.plasma-online.de/english/identify/picture/pcchips.html
Chipset name | OEM of | used on mainboard
---------------+---------------------------+-----------------------------------------
HX Pro | ALi M1521/M1523 |
SX Pro | SiS 530/5595 | M598
AGP Pro PC-100 | VIA VT82C598AT/VT82C596B | M577
TX AGP Pro | SiS 5591/5595/6326 |
TX Two | ALi M1531/M1543 |
TX Pro | ALi M1531/M1543 | M560, M575
TX Pro II | SiS 5597/5598 | M571
TX Pro III | VIA VT82C580VPX/VT82C586B | M573
TX Pro IV | SiS 5591/5592 | M570
Top Gun | ALi Aladdin IV+ | M565
VIA GRA | VIA VT8501/VT82C596B | M858LMR
VX Pro | VIA VT82C580VP/VT82C586B |
VX Pro + | VIA VT82C580VPX/VT82C586B |
VX Pro II | UTron / HiNT UT801X |
VX two | VIA VT82C580VP/VT82C586B | Amptron PM-8600A
VX two | VIA VT82C580VPX/VT82C586B | Amptron PM-8600B
BXToo | VIA Apollo Pro | M760V, M761V
BXToo | VIA VT82C693/VT82C686A | M767V
BXPro | SiS 600/5595 | M747
BXCel | ALi M1621/M1543 | M726, M729
BXpert | VIA VT82C691/VT82C596 |
BXTel | VIA Apollo Pro | M730
Xcel 2000 | SiS 620/5595 | M741LMRT
Super TX | SiS 5597/5598 | ASUS SP97-V, SP98-N, Jetway J-TX98R2
Super TX | ALi M1531/M1543 |
Super TX | ALi M1541/M1543 | Biostar M5ALA, M5ALC, Pionex MBD-P5ABx
Super TX3 | SiS 5571 |
Super TX4 AGP | |
GFXcel | SiS 630 |
GFXpro | ALi M1631/M1535D |
T-Bird | SiS730S | M810
---------------+---------------------------+----------------------------------------
*SIS...
*Symphony...
*TI (Texas Instruments)...
*UMC...
*Unresearched:...
*VIA...
**VT82C570M Apollo Master, Green Pentium/P54C <06/22/95
***Info:
The VT82C570M Apollo Master is a high performance, cost-effective and
energy efficient chip set for the implementation of PCI/ISA desktop
and notebook personal computer systems based on the 64-bit
P54C/Pentium/K5/M1 super-scalar processors. Either 3.3v or 5v CPU and
cache interface is supported up to 66Mhz CPU external bus speed (with
CPU internal speed up to 150Mhz and above). In either case, DRAM, PCI
and ISA bus runs at 5v voltage level.
The VT82C570M chip set consists of the VT82C575M system controller,
the VT82C576M PCI bus controller with integrated master mode
Enhanced-IDE controller, and two instances of the VT82C577M data
buffers. The CPU bus is minimally loaded with only the CPU, secondary
cache and the chip set. The VT82C577M data buffers isolate the CPU bus
from the DRAM, PCI and ISA bus so that CPU and cache operation may run
reliably at the high frequencies demanded by today's processors. The
chip set also interfaces directly with the VT82C416 integrated clock
generator, real time clock with extended CMOS (128 byte) and keyboard
controller with PS2 mouse support. A complete main board can be
implemented with only ten TTLs. Please refer to Figure 1 for the
system block diagram.
The VT82C570M supports eight banks of DRAMs up to 512MB. The DRAM
controller supports Standard Page Mode DRAM, EDO-DRAM and Burst
EDO-DRAM in a flexible mixed/match manner. The eight banks of DRAM
are grouped into four pairs with an arbitrary mixture of
256K/512K/1M/2M/4M/8M/16MxN DRAMs. Zero, one or both banks may be
populated in each pair with either 32bit or 64bit data width.
The secondary (L2) cache is based on Burst Synchronous (Pipelined or
non-pipelined) SRAM, asynchronous SRAM or cache module from 128KB to
2MB. For burst synchronous SRAMs, 3-1-1-1 timing can be achieved for
both read and write transactions at 66Mhz. For standard SRAMs, 3-2-2-2
and 4-2-2-2 timing can be achieved for interleaved read and write
transactions at 66Mhz. Four levels of CPU/cache to DRAM write buffers
with concurrent write-back capability are included in the VT82C577M
data buffer chips to speed up the cache read and write miss
cycles. For primary cache fill cycles that result in secondary cache
misses, the primary and secondary caches are filled up concurrently to
further enhance the performance.
***Configurations:...
***Features:...
**VT82C580VP Apollo VP, Pentium/M1/K5 PCI/ISA System <02/15/96...
**VT82C580VPX Apollo VPX, VPX/97, Pentium with 66/75MHz Bus <01/09/97...
**VT82C590 Apollo VP2, VP2/97, Single-Chip Pentium 66MHz <01/10/97...
**VT82C597/AT Apollo VP3, Single-Chip for Pentium with AGP <10/03/97...
**VT82C598MVP Apollo MVP3,Single-Chip 66/75/83/100MHz & AGP <09/22/97...
**VT8501 Apollo MVP4,Single-Chip 66-100MHz & AGP <11/04/98...
**VT82C680 Apollo P6, Pentium-Pro Chip Set <08/30/96
***Notes:...
***Info:...
***Configurations:...
***Features:...
**Support chips:
**VT82C505 Pentium/486 VL to PCI Bridge <05/30/94...
**VT82C586/A/B PCI Integrated Peripheral Controller <10/13/96...
**VT82C596/A Mobile PCI Integrated Peripheral Controller <11/05/97...
**VT82C686A/B PCI Super-I/O Integrated Peripheral Ctrl. <02/10/98...
**Later P-Pro/II/III/Celeron...
**Later AMD...
**Other...
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