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**82496/491 Cache Controller / Cache RAM (for P5 Pentium) 03/22/93
***Notes:...
***Info:
The 82496 Cache Controller and multiple 82491 Cache SRAMs combine with
the Pentium processor to form a CPU Cache chip set designed for high
performance servers and function-rich desktops. The high speed
interconnect between the CPU and cache components has been optimized
to provide zero-wait state operation. This CPU Cache chip set is
fully compatible with existing software, and has new data integrity
features for mission critical applications.
The 82496 cache controller implements the MESI write-back protocol for
full multiprocessing support. Dual ported buffers and registers allow
the 82496 to concurrently handle CPU bus, memory bus, and internal
cache operation for maximum performance.
The 82491. is a customized high-performance SRAM that supports 32, 64,
and 128-bit wide memory bus widths, 16, 32, and 64 byte line sizes,
and optional sectoring. The data path between the CPU bus and memory
bus is separated by the 82491, allowing the CPU bus to handshake
synchronously, asynchronously, or with a strobed protocol, and
allowing concurrent CPU bus and memory bus operations.
***Configurations:...
***Features:...
**82497/492 Cache Controller / Cache RAM (for P54 Pentium) <Nov94...
**82498/493 Cache Controller / Cache RAM (for P54 Pentium) <Nov94...
**
**Later chipsets (basic spec):
**440 series:...
**450NX (?) 06/29/98:...
**????? (Profusion) c:99...
**800 series...
*Headland/G2...
*HMC (Hulon Microelectronics)...
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*OPTi...
**82C750 Vendetta [no datasheet] ?
***Notes:...
**82c801 SCWB2 DX Single Chip Solution c:92...
**82C802 SCWB2 PC/AT Single Chip [no datasheet] ?...
**82C802G/GP System/Power Management Controller (cached) c:93...
**82C895 System/Power Management Controller (cached) c:Sep94...
**82C898 System/Power Management Controller (non-cache)c:Nov94...
**
**Support Chips:
**82C601/2 Buffer Devices <Nov94...
**82C822 PCIB (VLB-to-PCI bridge) c:94...
**Other:...
*PC CHIPS/Amptron/Atrend/ECS/Elpina/etc...
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*Unresearched:...
*VIA...
**VT82C680 Apollo P6, Pentium-Pro Chip Set <08/30/96
***Notes:...
***Info:
The VT82C680 Apollo-P6 is a high performance, cost-effective and
energy efficient chip set for the implementation of PCI/ISA desktop
and notebook personal computer systems based on the 64 bit Intel
Pentium-Pro super-scalar processors. The chipset supports multi-
Pentium-Pro configuration with Intel GTL+ driver and receiver inter-
face up to 66 MHz external CPU bus speed. The chipset supports the
Pentium-Pro CPU multi-phase bus protocols for split transactions, four
level deep in-order queue and deferred transactions for optimal CPU
throughput.
The VT82C680 chip set consists of the VT82C685 system controller, the
VT82C687 data buffer and the VT82C586 PCI to ISA bridge. The VT82C680
supports six banks of DRAMs up to 1 GB. The DRAM controller supports
Standard Page Mode DRAM, EDO-DRAM, Burst EDO-DRAM and Synchronous DRAM
in a flexible mixed/match manner. The Burst-EDO and Synchronous DRAM
allows zero wait state bursting between the DRAM and the VT82C687 data
buffers at 66 MHz. The six banks of DRAM allow arbitrary mixture of
1M/2M/4M/8M/16MxN DRAMs with optional bank-by-bank ECC and parity
support. The chipset supports sixteen level (quadwords) of CPU to DRAM
write buffers and sixteen level (quadwords) of DRAM to CPU read
buffers to maximize the CPU bus and DRAM utilization. The peak data
transfer rate for the EDO and Synchronous DRAM (or Burst EDO) DRAMs is
266 MB/s and 532 MB/s, respectively.
The VT82C680 supports 3.3/5v 32 bit PCI bus with 64 bit to 32 bit data
conversion. Sixteen levels (doublewords) of post write buffers are
included to allow for concurrent CPU and PCI operation. Consecutive
CPU addresses are converted into burst PCI cycles with Byte merging
capability for optimal CPU to PCI throughput. For PCI master
operation, sixteen levels (doublewords) of post write buffers and
thirty-two levels (doublewords) of prefetch buffers are included for
concurrent PCI bus and DRAM/cache accesses. The chipset also supports
enhanced PCI bus commands such as Memory-Read-Line,
Memory-Read-Multiple and Memory-Write-Invalid commands to minimize
snoop overhead. In addition, the chipset supports advanced features
such as snoop ahead, snoop filtering, CPU write-back forward to PCI
master and CPU write-back merged with PCI post write buffers to
minimize PCI master read latency and DRAM utilization. The VT82C586
PCI to ISA bridge supports four levels (doublewords) of line buffers,
type F DMA transfers and delay transaction to allow efficient PCI bus
utilization (PCI-2.1 compliant). The VT82C586 also includes integrated
keyboard controller with PS2 mouse support, integrated DS12885 style
real time clock with extended 128 Byte CMOS RAM, integrated master
mode enhanced IDE controller with full scatter and gather capability
and extension to 33 MB/sec UltraDMA-33 transfer rate, integrated USB
interface with root hub and two function ports with built-in physical
layer transceiver, and OnNow/ACPI compliant advanced configuration and
power management interface. A complete main board can be implemented
with only six TTLs.
The VT82C680 is ideal for high performance, high quality, high energy
efficient and high integration desktop and notebook PCI/ISA computer
systems.
***Configurations:...
***Features:...
**Support chips:
**VT82C505 Pentium/486 VL to PCI Bridge <05/30/94...
**VT82C586/A/B PCI Integrated Peripheral Controller <10/13/96...
**VT82C596/A Mobile PCI Integrated Peripheral Controller <11/05/97...
**VT82C686A/B PCI Super-I/O Integrated Peripheral Ctrl. <02/10/98...
**Later P-Pro/II/III/Celeron...
**Later AMD...
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