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*_IBM...
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*AMD . . . . . . . [no datasheets, some info]...
*Chips & Technologies...
*Contaq  . . . . . [no datasheets, some info]...
*Efar Microsystems [no datasheets, some info]...
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*Faraday...
*Forex . . . . . . [List only, no datasheets found]...
*Intel...
**800 series
***810         (Whitney)       04/26/99...
***810L        (Whitney)       04/26/99...
***810-DC100   (Whitney)       04/26/99...
***810e        (Whitney)       09/27/99...
***810e2       (Whitney)       01/03/01...
***815         (Solano)        06/19/00...
***815e        (Solano-2)      06/19/00...
***815em       (Solano-?)      10/23/00...
***815ep       (Solano-3)      c:Nov'00...
***815p        (Solano-3)      c:Mar'01...
***815g        (Solano-3)      c:Sep'01...
***815eg       (Solano-3)      c:Sep'01...
***820         (Camino)        11/15/99...
***820e        (Camino-2)      06/05/00...
***830M        (Almador)       07/30/01...
***830MP       (Almador)       07/30/01...
***830MG       (Almador)       07/30/01...
***840         (Carmel)        10/25/99...
***845         (Brookdale)     09/10/01...
***845MP       (Brookdale-M)   03/04/02...
***845MZ       (Brookdale-M)   03/04/02...
***845E        (Brookdale-E)   05/20/02...
***845G        (Brookdale-G)   05/20/02...
***845GL       (Brookdale-GL)  05/20/02...
***845GE       (Brookdale-GE)  10/07/02...
***845PE       (Brookdale-PE)  10/07/02...
***845GV       (Brookdale-GV)  10/07/02...
***848P        (Breeds Hill)   c:Aug'03...
***850         (Tehama)        11/20/00...
***850E        (Tehama-E)      05/06/02...
***852GM       (Montara-GM)    01/14/03...
***852GMV      (Montara-GM)    ???...
***852PM       (Montara-GM)    06/11/03...
***852GME      (Montara-GM)    06/11/03...
***854         (?)             04/11/05...
***855GM       (Montara-GM)    03/12/03...
***855GME      (Montara-GM)    03/12/03...
***855PM       (Odem)          03/12/03...
***860         (Colusa)        05/21/01...
***865G        (Springdale)    05/21/03...
***865PE       (Springdale-PE) 05/21/03...
***865P        (Springdale-P)  05/21/03...
***865GV       (Springdale-GV) c:Sep'03...
***875P        (Canterwood)    04/14/03...
*Headland/G2...
*HMC (Hulon Microelectronics)...
*Logicstar...
*Motorola...
*OPTi...
*PC CHIPS/Amptron/Atrend/ECS/Elpina/etc...
*SIS...
**5597/5598      (Jedi)    Pentium PCI/ISA Chipset           <04/15/97
***Info:...
***Configurations:...
***Features:...
**530/5595       (Sinbad) Host, PCI, 3D Graphics & Mem. Ctrl.<11/10/98...
**540            (Spartan) Super7 2D/3D Ultra-AGP Single C.S.<11/30/99...
**55x            SoC (System-on-chip)                        <03/14/02...
**
**Support chips:
**85C206     Integrated Peripheral Controller [no datasheet]         ?...
**5595       Pentium PCI System I/O                          <12/24/97...
**950        LPC I/O                                         <07/16/99...
**Other:...
**PII/III/Pro...
**Athlon etc...
*Symphony...
*TI (Texas Instruments)...
*UMC...
*Unresearched:...
*VIA...
**SL9020   Data Controller                                      <Jan90
***Info:...
***Versions:...
***Features:...
**SL9025   Address Controller                                   <Jan90...
**SL9030   Integrated Peripheral Controller                     <Jan90...
**SL9090/A Universal PC/AT Clock Chip                           <oct88...
**SL9095   Power  Management Unit                                    ?...
**SL9151   80286 Page Interleave Memory Controller (16-25MHz)        ?...
**SL9250   80386SX Page Mode Memory Controller (16/20MHz 8MB)        ?...
**SL9251   80386SX Page Interleave Memory Controller         <04/13/90...
**SL9252   80386SX System and Memory Controller              <06/12/90...
**SL9350   80386DX Page Mode Memory Controller (16-25MHz 16MB)       ?...
**SL9351   80386DX Page Interleave Memory Controller (33MHz)         ?...
**SL9352   80386DX System and Memory Controller              <06/12/90...
**SLXXXX   Other chips...
**
**VT82C470     "Jupiter", Chip Set (w/o cache) 386 [no datasheet]    ?
**VT82C475     "Jupiter", Chip Set (w/cache) 386   [no datasheet]    ?
**VT82C486/2/3 "GMC chipset"            [no datasheet, some info]    ?...
**VT82C495/480 "Venus" Chip Set                    [no datasheet]    ?
**VT82C495/491 ? EISA Chip Set          [no datasheet, some info]  <93...
**VT82C496G    Pluto, Green PC 80486 PCI/VL/ISA System       <05/30/94...
**VT82C530MV   3.3V Pentium chipset [no datasheet, some info]<05/30/94...
**VT82C570M    Apollo Master, Green Pentium/P54C             <06/22/95...
**VT82C580VP   Apollo VP,  Pentium/M1/K5 PCI/ISA System      <02/15/96...
**VT82C580VPX  Apollo VPX, VPX/97, Pentium with 66/75MHz Bus <01/09/97...
**VT82C590     Apollo VP2, VP2/97, Single-Chip Pentium 66MHz <01/10/97...
**VT82C597/AT  Apollo VP3, Single-Chip for Pentium with AGP  <10/03/97...
**VT82C598MVP  Apollo MVP3,Single-Chip 66/75/83/100MHz & AGP <09/22/97...
**VT8501       Apollo MVP4,Single-Chip 66-100MHz & AGP       <11/04/98
***Notes:...
***info:...
***Configurations:...
***Features:
o   General
    - 492 BGA Package (35mm x 35mm )
    - 2.5 Volt +/- 0.2V Core
    - Supports separately powered 3.3V tolerant interface to CPU and  
      Memory
    - Supports separately powered 5.0V tolerant interface to PCI bus 
      and Video interface
    - 2.5V, 0.25um, high speed / low power CMOS process
    - PC-98/99 compatible using VIA VT82C686A (352-pin BGA) south 
      bridge chip
    - 66 / 100 MHz Operation
        CPU      Internal DRAM /   PCI     Comments
                 AGP      VGC
        100 MHz  66 MHz   100 MHz  33 MHz  synchronous 
                                           (DRAM uses CPU clock)
        66  MHz  66 MHz   66  MHz  33 MHz  synchronous 
                                           (DRAM uses CPU clock)
        66  MHz  66 MHz   100 MHz  33 MHz  Up pseudo-synchronous 
                                           (DRAM uses MEM clock)
o   Socket 7 Host Interface
    - Supports all Socket-7 / Super-7 processors including 64-bit 
      Intel Pentium / Pentium with MMX , AMD 6K86 (K6 and K6-2), 
      Cyrix/IBM 6x86 / 6x86MX, IDT/Centaur C6, and Rise MP6 CPUs
    - 66 / 100 MHz CPU "Front Side Bus"
    - Supports 3.3V and sub-3.3V interface to CPU
    - Built-in de-skew PLL (Phase Lock Loop) circuitry for optimal 
      skew control within and between clocking regions
    - Cyrix/IBM 6x86 linear burst support
    - AMD K6 and K6-2 write allocation support
    - Supports CPU-to-DRAM write combining
    - System management interrupt, memory remap and stop clock 
      mechanisms
o   Advanced L2 Cache
    - Direct map write-back or write-through secondary cache
    - Pipelined burst synchronous SRAM (PBSRAM) cache support
    - Flexible cache size:  0K / 256K / 512K / 1M / 2MB
    - 32 byte line size to match the primary cache
    - Integrated 8-bit tag comparator
    - 3-1-1-1-1-1-1-1 back to back read timing for PBSRAM accesses 
      up to 100 MHz
    - Tag timing optimized (less than 4ns setup time) to allow 
      external tag SRAM implementation for most flexible cache
      organization
    - Sustained 3 cycle write access for PBSRAM access or CPU to 
      DRAM & PCI bus post write buffers up to 100 MHz
    - Supports CPU single read cycle L2 allocation
    - System and video BIOS cacheable and write-protect
    - Programmable cacheable region
o   Internal Accelerated Graphics Port (AGP) Controller
    - AGP v2.0 compliant for 1x and 2x transfer modes
    - Pipelined split-transaction long-burst transfers up to 
      533 MB/sec
    - Eight level read request queue
    - Four level posted-write request queue
    - Thirty-two level (quadwords) read data FIFO (128 bytes)
    - Sixteen level (quadwords) write data FIFO (64 bytes)
    - Intelligent request reordering for maximum AGP bus utilization
    - Supports Flush/Fence commands
    - Graphics Address Relocation Table (GART)
    - One level TLB structure
    - Sixteen entry fully associative page table
    - LRU replacement scheme
    - Independent GART lookup control for host / AGP / PCI master 
      accesses
    - Windows 95 OSR-2 VXD and integrated Windows 98 / NT5 miniport 
      driver support
o   Concurrent PCI Bus Controller
    - PCI bus is synchronous / pseudo-synchronous to host CPU bus
    - 33 MHz operation on the primary PCI bus
    - Supports up to five PCI masters
    - Peer concurrency
    - Concurrent multiple PCI master transactions; i.e., allow PCI 
      masters from both PCI buses active at the same time
    - Zero wait state PCI master and slave burst transfer rate
    - PCI to system memory data streaming up to 132Mbyte/sec
    - PCI master snoop ahead and snoop filtering
    - Six levels (double-words) of CPU to PCI posted write buffers
    - Byte merging in the write buffers to reduce the number of PCI 
      cycles and to create further PCI bursting possibilities
    - Enhanced PCI command optimization (MRL, MRM, MWI, etc.)
    - Forty-eight levels (double-words) of post write buffers from 
      PCI masters to DRAM
    - Sixteen levels (double-words) of prefetch buffers from DRAM 
      for access by PCI masters
    - Supports L1/L2 write-back forward to PCI master read to 
      minimize PCI read latency
    - Supports L1/L2 write-back merged with PCI master post-write to 
      minimize DRAM utilization
    - Delay transaction from PCI master reading DRAM
    - Read caching for PCI master reading DRAM
    - Transaction timer for fair arbitration between PCI masters 
      (granularity of two PCI clocks)
    - Symmetric arbitration between Host/PCI bus for optimized 
      system performance
    - Complete steerable PCI interrupts
    - PCI-2.2 compliant, 32 bit 3.3V PCI interface with 5V tolerant 
      inputs
o   High-Performance DRAM Controller
    - 64-bit DRAM interface synchronous with host CPU (66//100 MHz) 
      or internal Memory Clock (100 MHz)
    - Concurrent CPU and AGP access
    - Supports both standard PC100 and "Virtual Channel" PC100 
      SDRAMs as well as FPG and EDO DRAMs
    - Different DRAM types (FPG, EDO, and SDRAM) may be used in 
      mixed combinations
    - Different DRAM timing for each bank
    - Dynamic Clock Enable (CKE) control for SDRAM power reduction
    - Mixed 1M / 2M / 4M / 8M / 16MxN DRAMs
    - 6 banks up to 768MB DRAMs
    - Flexible row and column addresses
    - 64-bit data width only
    - 3.3V DRAM interface
    - Programmable I/O drive capability for MA, command, and MD 
      signals
    - Optional bank-by-bank ECC (single-bit error correction and 
      multi-bit error detection) or EC (error checking only) for 
      DRAM integrity
    - Two-bank interleaving for 16Mbit SDRAM support
    - Two-bank and four bank interleaving for 64Mbit SDRAM support
    - Supports maximum 8-bank interleave (i.e., 8 pages open 
      simultaneously); banks are allocated based on LRU
    - Seamless DRAM command scheduling for maximum DRAM bus 
      utilization (e.g., precharge other banks while accessing the 
      current bank)
    - Four cache lines (16 quadwords) of CPU/cache to DRAM write 
      buffers
    - Four quadwords of CPU/cache to DRAM read prefetch buffers
    - Concurrent DRAM writeback
    - Read around write capability for non-stalled CPU read
    - Burst read and write operation
    - 5-2-2-2-2-2-2-2 back-to-back accesses for EDO DRAM
    - 6-1-1-1-2-1-1-1 back-to-back accesses for SDRAM
    - BIOS shadow at 16KB increment
    - Decoupled and burst DRAM refresh with staggered RAS timing
    - Programmable refresh rate and refresh on populated banks only
    - CAS before RAS or self refresh
o   Sophisticated Power Management Features
    - Independent clock stop controls for CPU / SDRAM, Internal AGP 
      and PCI bus
    - PCI and AGP bus clock run and clock generator control
    - Suspend power plane preserves memory data
    - Suspend-to-DRAM and Self-Refresh operation
    - Dynamic clock gating for internal functional blocks for power 
      reduction during normal operation
    - Low-leakage I/O pads
o   General Graphic Capabilities
    - 64-bit Single Cycle 2D/3D Graphics Engine
    - Supports 2 to 8 Mbytes of Frame Buffer located in System Memory
    - Real Time DVD MPEG-2 and AC-3 Playback
    - Video Processor
    - I2C Serial Interface
    - Integrated 24-bit 230MHz True Color DAC
    - Extended Screen Resolutions up to 1600x1200
    - Extended Text Modes 80 or 132 columns by 25/30/43/60 rows
    - DirectX 6 and OpenGL ICD API
o   High Performance rCADE3D Accelerator
    - 32 entry command queue, 32 entry data queue
    - 4Kbyte texture cache with over 90% hit rates
    - Pipelined Setup/Texturing/Rendering Engines
    - DirectDraw acceleration
    - Multiple buffering and page flipping
    o Setup Engine
    - 32-bit IEEE floating point input data
    - Slope and vertex calculations
    - Back facing triangle culling
    - 1/16 sub-pixel positioning

    o Rendering Engine
    - High performance single pass execution
    - Diffused and specula lighting
    - Gouraud and flat shading
    - Anti-aliasing including edge, scene, and super-sampling
    - OpenGL compliant blending for fog and depth-cueing
    - 16-bit Z-buffer
    - 8/16/32 bit per pixel color formats

    o Texturing Engine
    - D3D compressed texture formats DXT1 and DXT2
    - Anisotropic texture filtering
    - 1/2/4/8-bits per pixel compact palletized textures
    - 16/32-bits per pixel quality non-palletized textures
    - Pallet formats in ARGB 565, 1555, or 444
    - Tri-linear, bi-linear, and point-sampled filtering
    - Mip-mapping with multiple Level-Of-Detail (LOD) calculations 
      and perspective correction
    - Color keying for translucency

    o 2D GUI Engine
    - 8/15/16/24/32-bits per pixel color formats
    - 256 Raster Operations (ROPs)
    - Accelerated drawing:  BitBLTs, lines, polygons, fills, 
      patterns, clipping, bit masking
    - Panning, scrolling, clipping, color expansion, sprites
    - 32x32 and 64x64 Hardware Cursor
    - DOS graphics and text modes
o   DVD
    - Hardware-Assisted MPEG-2 Architecture for DVD with AC-3
    - Simultaneous motion compensation and front-end processing 
      (parsing, decryption and decode)
    - Supports full DVD 1.0, VCD 2.0 and CD-Karaoke
    - Microsoft DirectShow 2.x native support, backward compatible to 
      MCI
    - No additional frame buffer requirements
    - Dynamic frame and field de-interlace filtering for high quality 
      playback on VGA monitors (Bob and Weave)
    - Tamper-proof software CSS implementation
    - Freeze, Fast-Forward, Slow Motion, Reverse
    - Pan-and-Scan support for 16:9 sequence
o   Video Processor
    - On-chip Color Space Converter (CSC)
    - Anti-tearing via two frame buffer based capture surfaces
    - Minifier for video stream compression and filtering
    - Horizontal/vertical interpolation with edge recovery
    - Dual frame buffer apertures for independent memory access for 
      graphics and video
    - YUV 4:2:2/4:1:1/4:2:0 and RGB formats
    - Capture / ZV Port to MPEG and video decoder
    - Vertical Blank Interval for Intercast
    - Overlay differing video and graphic color depths
    - Display two simultaneous video streams from both internal AGP 
      and Capture / ZV Port
    - Two scalers and Color Space Converters (CSC) for independent 
      windows
o   Digital Flat Panel (DFP) Interface
    - 85MHz DFP interface supports 1024x768 panels
    - Allows external TMDS transmitter for advanced panel interfaces
o   Testability
    - Build-in NAND-tree pin scan test capability

**VT82C680     Apollo P6, Pentium-Pro Chip Set               <08/30/96...
**Support chips:
**VT82C505     Pentium/486 VL to PCI Bridge                  <05/30/94...
**VT82C586/A/B PCI Integrated Peripheral Controller          <10/13/96...
**VT82C596/A   Mobile PCI Integrated Peripheral Controller   <11/05/97...
**VT82C686A/B  PCI Super-I/O Integrated Peripheral Ctrl.     <02/10/98...
**Later P-Pro/II/III/Celeron...
**Later AMD...
**Other...
*VLSI...
*Western Digital...
*Winbond...
*ZyMOS...
*General Sources:...

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