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**82498/493   Cache Controller / Cache RAM (for P54 Pentium)    <Nov94
***Notes:...
***Info:...
***Configurations:...
***Features:...
**
**Later chipsets (basic spec):
**440 series:...
**450NX  (?)            06/29/98:...
**?????  (Profusion)    c:99...
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**HT18          80386SX Single Chip                            c:Sep91
***Info:...
***Configurations:...
***Features:...
**HT21          386SX/286 Single Chip (20 MHz)                 c:Aug91...
**HT22          386SX/286 Single Chip (25 MHz)                 c:Sep91...
**HT25          3-volt Core Logic for 386SX                    c:Dec92...
**HT35          Single-Chip Peripheral Controller [partial info]     ?...
**HTK320        386DX Chip Set                                 c:Sep91...
**HTK340        "Shasta" 486 Chip Set                          c:Jun92...
**Support Chips:
**HT44          Secondary Cache                                c:Jun92...
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*VIA...
**VT82C590     Apollo VP2, VP2/97, Single-Chip Pentium 66MHz <01/10/97
***Info:
The  VT82C590 Apollo-VP2  is  a high  performance, cost-effective  and
energy efficient  chip set for  the implementation of  PCI/ISA desktop
and   notebook  personal   computer  systems   based  on   the  64-bit
Pentium/AMD5K86/AMD6K86/Cyrix6X86 super-scalar processors.

The  Apollo-VP2 chip set  consists of  the VT82C595  system controller
(328 pin BGA) and the VT82C586B  PCI to ISA bridge (208 pin PQFP). The
VT82C595 system  controller provides superior  performance between the
CPU, optional synchronous cache, DRAM  and the PCI bus with pipelined,
burst and concurrent operation. For pipelined burst synchronous SRAMs,
3-1-1-1-1-1-1-1  timing  can  be  achieved  for both  read  and  write
transactions at 66  Mhz. Four cache lines (16  quadwords) of CPU/cache
to  DRAM  write  buffers  with concurrent  write-back  capability  are
included in the chip to speed up the cache read and write miss cycles.

The  VT82C595  supports six  banks  of DRAMs  up  to  512KB. The  DRAM
controller supports Standard Page  Mode DRAM, EDO DRAM and Synchronous
DRAM in a flexible mix  / match manner. The Synchronous DRAM interface
allows zero wait state bursting  between the DRAM and the data buffers
at  66Mhz. The  six banks  of  DRAM can  be composed  of an  arbitrary
mixture of 1M / 2M / 4M / 8M / 16MxN DRAMs. Each bank may be populated
with  either 32bit  or 64bit  data  width.  The  DRAM controller  also
supports  optional  ECC  (single-bit  error correction  and  multi-bit
detection) capability.

The VT82C595  supports 3.3 / 5V  32-bit PCI bus with  64-bit to 32-bit
data conversion.  Five levels (doublewords) of post  write buffers are
included to  allow for concurrent  CPU and PCI  operation. Consecutive
CPU addresses  are converted into  burst PCI cycles with  byte merging
capability  for  optimal  CPU   to  PCI  throughput.  For  PCI  master
operation, forty-eight levels (doublewords)  of post write buffers and
sixteen  levels (doublewords)  of  prefetch buffers  are included  for
concurrent PCI bus and  DRAM/cache accesses. The chipset also supports
enhanced  PCI  bus  commands  such as  Memory-Read-Line,  Memory-Read-
Multiple   and  Memory-Write-Invalid   commands   to  minimize   snoop
overhead. In addition, the  chipset supports advanced features such as
snoop ahead, snoop filtering, L1  write-back forward to PCI master and
L1  write-back merged  with PCI  post  write buffers  to minimize  PCI
master read  latency and  DRAM utilization. The  VT82C586B PCI  to ISA
bridge supports four levels (doublewords)  of line buffers, type F DMA
transfers and delay transaction to allow efficient PCI bus utilization
and  (PCI-2.1 compliant).  The VT82C586B  also includes  an integrated
keyboard controller  with PS2 mouse support,  integrated DS12885 style
real time  clock with  extended 256 byte  CMOS RAM,  integrated master
mode enhanced  IDE controller with full scatter  and gather capability
and  extension to  UltraDMA-33 /  ATA-33 for  33MB/sec  transfer rate,
integrated USB  interface with  root hub and  two function  ports with
built-in  physical layer  transceivers, Distributed  DMA  support, and
OnNow  / ACPI  compliant advanced  configuration and  power management
interface.  A complete  main board  can be  implemented with  only six
TTLs.   

The VT82C590 chipset is ideal for high performance, high quality, high
energy  efficient and  high integration  desktop and  notebook PCI/ISA
computer systems.

***Configurations:...
***Features:...
**VT82C597/AT  Apollo VP3, Single-Chip for Pentium with AGP  <10/03/97...
**VT82C598MVP  Apollo MVP3,Single-Chip 66/75/83/100MHz & AGP <09/22/97...
**VT8501       Apollo MVP4,Single-Chip 66-100MHz & AGP       <11/04/98...
**VT82C680     Apollo P6, Pentium-Pro Chip Set               <08/30/96...
**Support chips:
**VT82C505     Pentium/486 VL to PCI Bridge                  <05/30/94...
**VT82C586/A/B PCI Integrated Peripheral Controller          <10/13/96...
**VT82C596/A   Mobile PCI Integrated Peripheral Controller   <11/05/97...
**VT82C686A/B  PCI Super-I/O Integrated Peripheral Ctrl.     <02/10/98...
**Later P-Pro/II/III/Celeron...
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