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*Forex . . . . . . [List only, no datasheets found]...
*Intel...
**82498/493   Cache Controller / Cache RAM (for P54 Pentium)    <Nov94
***Notes:...
***Info:...
***Configurations:...
***Features:...
**
**Later chipsets (basic spec):
**440 series:...
**450NX  (?)            06/29/98:...
**?????  (Profusion)    c:99...
**800 series...
*Headland/G2...
*HMC (Hulon Microelectronics)...
*Logicstar...
*Motorola...
*OPTi...
*PC CHIPS/Amptron/Atrend/ECS/Elpina/etc...
**Notes:
You eventually get  to know when a  board is made by PC  Chips just by
looking at it.
 
Here is a test:
1.  No manufacture name, or one of the above.
2.  If the board has a lots of components that sound like a well known 
    part but aren't the well known part. i.e. 'HX Pro' instead of 
    '430HX'
3a. A really good feature set where you think, that's exactly what I'm 
    looking for.
 b. The features don't really work as intended. 
4.  The price is fantastic.
5.  Its disappointing on closer examination.

PC Chips is  renowned for making crap products. Some  are actually not
too bad, they're no worse than  your average brand. However some are a
nightmare either by design or  just poorly made. Fake components glued
on is not  uncommon. Fake labels over other components.  PCB's so thin
they require low insertion force ISA connectors, every trick to save a
few $.

**Early Chipsets:...
**Later Chipsets:...
*SIS...
*Symphony...
*TI (Texas Instruments)...
*UMC...
*Unresearched:...
*VIA...
**VT82C580VPX  Apollo VPX, VPX/97, Pentium with 66/75MHz Bus <01/09/97
***Notes:...
***Info:...
***Configurations:...
***Features:
o   Flexible CPU Interface
    - Supports 64-bit Pentium, AMD 5k86, AMD 6k86 and Cyrix 6x86 CPUs
    - CPU external bus speed up to 75 MHz (asynchronous) or 66MHz 
      (synchronous) (internal 200Mhz and above)
    - Supports CPU internal write-back cache
    - System management interrupt, memory remap and STPCLK mechanism
    - Cyrix 6x86 linear burst support
    - CPU NA# / Address pipeline capability
o   Low Cost
    - PQFP packaging for low-cost implementation of 64-bit Pentium-
      CPU, 64-bit system memory, and 32-bit PCI
    - VT82C580 Apollo VPX Chipset:  VT82C585VPX system controller and 
      VT82C587VP Data Buffers
    - VT82C586B includes UltraDMA-33 EIDE, USB, and Keyboard / Mouse 
      Interfaces plus RTC / CMOS
    - Six TTLs for a complete main board implementation
o   PCI/ISA Green PC Ready
    - Supports 3.3V or 5V interface to CPU, system memory, and / or 
      PCI bus
    - Supports CPUs with internal voltages below 3.3V
    - PC-97 compatible using VT82C586B South Bridge with ACPI 
      Power Management
o   Advanced Cache Controller
    - Direct map write back or write through secondary cache
    - Pipelined burst synchronous SRAM (PBSRAM) cache support
    - Flexible cache size: 0K/256K/512K/1M/2MB
    - 32 byte line size to match the primary cache
    - Integrated 10-bit tag comparator
    - 3-1-1-1 read/write timing for PBSRAM access at 66/75 MHz
    - 3-1-1-1-1-1-1-1 back to back read timing for PBSRAM access 
      at 66/75 MHz
    - Sustained 3 cycle write access for PBSRAM access or CPU to 
      DRAM and PCI bus post write buffers at 66/75 MHz
    - Data streaming for simultaneous primary and secondary cache 
      line fill
    - System and video BIOS cacheable and write-protect
    - Programmable cacheable region and cache timing
o   Fast DRAM Controller
    - Fast Page Mode/EDO/Synchronous-DRAM support in a mixed 
      combination
    - Mixed 1M/2M/4M/8M/16MxN DRAMs
    - 6 banks up to 512MB DRAMs
    - Flexible row and column addresses
    - 64-bit or 32-bit data width in arbitrary mixed combination
    - 3.3v and 5v DRAM without external buffers
    - Two-bank interleaving for 16Mbit SDRAM support
    - Two-bank and four bank interleaving for 64Mbit SDRAM support 
      (14 MA lines)
    - Four cache lines (16 quadwords) of CPU/cache to DRAM write 
      buffers
    - Concurrent DRAM writeback
    - Speculative DRAM access
    - Read around write capability for non-stalled CPU read
    - Burst read and write operation
    - 4-2-2-2 on page, 7-2-2-2 start page and 9-2-2-2 off page timing 
      for EDO DRAMs at 50/60 MHz
    - 5-2-2-2 on page, 8-2-2-2 start page and 11-2-2-2 off page timing 
      for EDO DRAMs at 66 MHz
    - 6-1-1-1 on page, 8-1-1-1 start page and 10-1-1-1 off page for 
      SDRAMs at 66 MHz
    - 5-2-2-2-3-1-2-2 back-to-back access for EDO DRAM at 66 MHz
    - 6-1-1-1-3-1-1-1 back-to-back access for SDRAM at 66 MHz
    - BIOS shadow at 16KB increment
    - Decoupled and burst DRAM refresh with staggered RAS timing
    - Programmable refresh rate, CAS-before-RAS refresh and refresh 
      on populated banks only
o   Intelligent PCI Bus Controller
    - 32 bit 3.3/5v PCI interface
    - Synchronous divide-by-two and asynchronous PCI bus interface
    - PCI master snoop ahead and snoop filtering
    - PCI master peer concurrency
    - Synchronous bus to CPU clock with divide-by-two from the CPU 
      clock
    - Automatic detection of data streaming burst cycles from CPU to 
      the PCI bus
    - Five levels (double-words) of CPU to PCI posted write buffers
    - Byte merging in the write buffers to reduce the number of PCI 
      cycles and to create further PCI bursting possibilities
    - Zero wait state PCI master and slave burst transfer rate
    - PCI to system memory data streaming up to 132Mbyte/sec
    - Forty-eight levels (double-words) of post write buffers from 
      PCI masters to DRAM
    - Sixteen levels (double-words) of prefetch buffers from DRAM 
      for access by PCI masters
    - Enhanced PCI command optimization (MRL, MRM, MWI, etc.)
    - Complete steerable PCI interrupts
    - Supports L1 write-back forward to PCI master read to minimize 
      PCI read latency
    - Supports L1 write-back merged with PCI master post-write to 
      minimize DRAM utilization
    - Provides transaction timer to fairly arbitrate between PCI 
      masters
    - PCI-2.1 compliant
o   Built-in nand-tree pin scan test capability
o   0.6um mixed voltage, high speed / low power CMOS process
o   VT82C585VPX:  208-pin PQFP Package
o   VT82C587VP:  100-pin PQFP Package

**VT82C590     Apollo VP2, VP2/97, Single-Chip Pentium 66MHz <01/10/97...
**VT82C597/AT  Apollo VP3, Single-Chip for Pentium with AGP  <10/03/97...
**VT82C598MVP  Apollo MVP3,Single-Chip 66/75/83/100MHz & AGP <09/22/97...
**VT8501       Apollo MVP4,Single-Chip 66-100MHz & AGP       <11/04/98...
**VT82C680     Apollo P6, Pentium-Pro Chip Set               <08/30/96...
**Support chips:
**VT82C505     Pentium/486 VL to PCI Bridge                  <05/30/94...
**VT82C586/A/B PCI Integrated Peripheral Controller          <10/13/96...
**VT82C596/A   Mobile PCI Integrated Peripheral Controller   <11/05/97...
**VT82C686A/B  PCI Super-I/O Integrated Peripheral Ctrl.     <02/10/98...
**Later P-Pro/II/III/Celeron...
**Later AMD...
**Other...
*VLSI...
*Western Digital...
*Winbond...
*ZyMOS...
*General Sources:...

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