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**82489DX Advanced Programmable Interrupt Controller 10/12/92
***Notes:...
***Info:...
***Versions:...
***Features:...
**82495DX/490DX DX CPU-Cache Chip Set <Sep91...
**82495XP/490XP Cache Controller / Cache RAM (for i860) 06/05/91...
**82496/491 Cache Controller / Cache RAM (for P5 Pentium) 03/22/93...
**82497/492 Cache Controller / Cache RAM (for P54 Pentium) <Nov94...
**82498/493 Cache Controller / Cache RAM (for P54 Pentium) <Nov94...
**
**Later chipsets (basic spec):
**440 series:...
**450NX (?) 06/29/98:...
**????? (Profusion) c:99...
**800 series...
*Headland/G2...
*HMC (Hulon Microelectronics)...
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*TI (Texas Instruments)...
*UMC...
**UM82C230 286AT MORTAR Chip Set <91
***Info:...
***Configurations:...
***Features:...
**UM82C210 386SX/286 AT Chip Set <91...
**UM82C3xx Twinstar & UM82C336F/N & UM82C39x [no datasheet] ?...
**UM82C380 386 HEAT PC/AT Chip Set <91...
**UM82C480 386/486 PC Chip Set c91...
**UM82C493/491 ??????????????? [no datasheet] ?...
**UM8498/8496 486 VL Chipset "Super Energy Star Green"[no dsheet]c94...
**UM8881/8886 HB4 PCI Chipset "Super Energy Star Green"[no dsheet]c94...
**UM8890 Pentium chipset [no datasheet] ?...
**
**Support Chips:
**UM82152 Cache Controller (AUStek A38152 clone) <91...
**UM82C852 Multi I/O For XT <91...
**UM82C206 Integrated Peripheral Controller <91...
**UM82c45x Serial/Parallel chips ?...
**Other chips:...
*Unresearched:...
*VIA...
**SL9XXX FlexSet family General information
The SL9XXX series seems to have been designed to work with the 80286,
80386SX and 80386DX, and is possibly compatible with the 80486. What-
ever CPU used, the chipset contains the following chips, known as the
"Core AT Logic chips":
SL9011 System Controller
SL9020 Data Controller (2x for 32bit 386DX)
SL9025 Address Controller
SL9030 Integrated Peripheral Controller
The memory controller is then selected based on the CPU. It appears
that the lineup originally consisted of the following chips, known as
"Personalized AT Logic":
SL9151 Page Interleave Memory (80286)
SL9250 Memory Controller (80386SX)
SL9350 Page Mode Memory Controller (80386DX)
Later updates were:
SL9251 Page Interleave Memory Controller (80386SX)
SL9351 Page Interleave Memory Controller (80386DX)
Further updates were:
SL9252 System and Memory Controller (80386SX)
SL9352 System and Memory Controller (80386DX)
As far as i can tell, these chips only require the addition of the
SL9020, or 2x in the case of the SL9352. The datasheets are quite
terse.
These parts and the whole design of the datasheets are very similar to
the chipsets released by Logicstar. I, however, cannot find any record
of a link between the companies. See *Logicstar for details.
**SL9011 System Controller (80286/80386SX/DX, 16/20/25MHz) <Jan90...
**SL9020 Data Controller <Jan90...
**SL9025 Address Controller <Jan90...
**SL9030 Integrated Peripheral Controller <Jan90...
**SL9090/A Universal PC/AT Clock Chip <oct88...
**SL9095 Power Management Unit ?...
**SL9151 80286 Page Interleave Memory Controller (16-25MHz) ?...
**SL9250 80386SX Page Mode Memory Controller (16/20MHz 8MB) ?...
**SL9251 80386SX Page Interleave Memory Controller <04/13/90...
**SL9252 80386SX System and Memory Controller <06/12/90...
**SL9350 80386DX Page Mode Memory Controller (16-25MHz 16MB) ?...
**SL9351 80386DX Page Interleave Memory Controller (33MHz) ?...
**SL9352 80386DX System and Memory Controller <06/12/90...
**SLXXXX Other chips...
**
**VT82C470 "Jupiter", Chip Set (w/o cache) 386 [no datasheet] ?
**VT82C475 "Jupiter", Chip Set (w/cache) 386 [no datasheet] ?
**VT82C486/2/3 "GMC chipset" [no datasheet, some info] ?...
**VT82C495/480 "Venus" Chip Set [no datasheet] ?
**VT82C495/491 ? EISA Chip Set [no datasheet, some info] <93...
**VT82C496G Pluto, Green PC 80486 PCI/VL/ISA System <05/30/94...
**VT82C530MV 3.3V Pentium chipset [no datasheet, some info]<05/30/94...
**VT82C570M Apollo Master, Green Pentium/P54C <06/22/95
***Info:
The VT82C570M Apollo Master is a high performance, cost-effective and
energy efficient chip set for the implementation of PCI/ISA desktop
and notebook personal computer systems based on the 64-bit
P54C/Pentium/K5/M1 super-scalar processors. Either 3.3v or 5v CPU and
cache interface is supported up to 66Mhz CPU external bus speed (with
CPU internal speed up to 150Mhz and above). In either case, DRAM, PCI
and ISA bus runs at 5v voltage level.
The VT82C570M chip set consists of the VT82C575M system controller,
the VT82C576M PCI bus controller with integrated master mode
Enhanced-IDE controller, and two instances of the VT82C577M data
buffers. The CPU bus is minimally loaded with only the CPU, secondary
cache and the chip set. The VT82C577M data buffers isolate the CPU bus
from the DRAM, PCI and ISA bus so that CPU and cache operation may run
reliably at the high frequencies demanded by today's processors. The
chip set also interfaces directly with the VT82C416 integrated clock
generator, real time clock with extended CMOS (128 byte) and keyboard
controller with PS2 mouse support. A complete main board can be
implemented with only ten TTLs. Please refer to Figure 1 for the
system block diagram.
The VT82C570M supports eight banks of DRAMs up to 512MB. The DRAM
controller supports Standard Page Mode DRAM, EDO-DRAM and Burst
EDO-DRAM in a flexible mixed/match manner. The eight banks of DRAM
are grouped into four pairs with an arbitrary mixture of
256K/512K/1M/2M/4M/8M/16MxN DRAMs. Zero, one or both banks may be
populated in each pair with either 32bit or 64bit data width.
The secondary (L2) cache is based on Burst Synchronous (Pipelined or
non-pipelined) SRAM, asynchronous SRAM or cache module from 128KB to
2MB. For burst synchronous SRAMs, 3-1-1-1 timing can be achieved for
both read and write transactions at 66Mhz. For standard SRAMs, 3-2-2-2
and 4-2-2-2 timing can be achieved for interleaved read and write
transactions at 66Mhz. Four levels of CPU/cache to DRAM write buffers
with concurrent write-back capability are included in the VT82C577M
data buffer chips to speed up the cache read and write miss
cycles. For primary cache fill cycles that result in secondary cache
misses, the primary and secondary caches are filled up concurrently to
further enhance the performance.
***Configurations:...
***Features:...
**VT82C580VP Apollo VP, Pentium/M1/K5 PCI/ISA System <02/15/96...
**VT82C580VPX Apollo VPX, VPX/97, Pentium with 66/75MHz Bus <01/09/97...
**VT82C590 Apollo VP2, VP2/97, Single-Chip Pentium 66MHz <01/10/97...
**VT82C597/AT Apollo VP3, Single-Chip for Pentium with AGP <10/03/97...
**VT82C598MVP Apollo MVP3,Single-Chip 66/75/83/100MHz & AGP <09/22/97...
**VT8501 Apollo MVP4,Single-Chip 66-100MHz & AGP <11/04/98...
**VT82C680 Apollo P6, Pentium-Pro Chip Set <08/30/96...
**Support chips:
**VT82C505 Pentium/486 VL to PCI Bridge <05/30/94...
**VT82C586/A/B PCI Integrated Peripheral Controller <10/13/96...
**VT82C596/A Mobile PCI Integrated Peripheral Controller <11/05/97...
**VT82C686A/B PCI Super-I/O Integrated Peripheral Ctrl. <02/10/98...
**Later P-Pro/II/III/Celeron...
**Later AMD...
**Other...
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