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**A note on VESA support of 486 chipsets.
Many chipsets state  that they support VESA local  bus.  In some cases
these actually  implement VLB somewhat  like PCI, where it  is entirly
decoupled from the CPU bus. Chipsets  that do not state they work with
VLB,  may  be found  on  motherboards  that  contain VLB  slots.   VLB
is  *basically*  The 486  CPU  pinout in  a  slot  form. Unless  these
m/boards contain  some additional  chips, there VLB  implementation is
directly coupled to the CPU.

**Datasheets:...
*_IBM...
*ACC Micro...
*ALD...
*ALi...
*AMD . . . . . . . [no datasheets, some info]...
*Chips & Technologies...
*Contaq  . . . . . [no datasheets, some info]...
*Efar Microsystems [no datasheets, some info]...
*ETEQ...
*Faraday...
*Forex . . . . . . [List only, no datasheets found]...
*Intel...
**82489DX       Advanced Programmable Interrupt Controller    10/12/92
***Notes:...
***Info:...
***Versions:...
***Features:...
**82495DX/490DX DX CPU-Cache Chip Set                           <Sep91...
**82495XP/490XP Cache Controller / Cache RAM (for i860)       06/05/91...
**82496/491     Cache Controller / Cache RAM (for P5 Pentium) 03/22/93...
**82497/492   Cache Controller / Cache RAM (for P54 Pentium)    <Nov94...
**82498/493   Cache Controller / Cache RAM (for P54 Pentium)    <Nov94...
**
**Later chipsets (basic spec):
**440 series:...
**450NX  (?)            06/29/98:...
**?????  (Profusion)    c:99...
**800 series...
*Headland/G2...
*HMC (Hulon Microelectronics)...
*Logicstar...
*Motorola...
*OPTi...
*PC CHIPS/Amptron/Atrend/ECS/Elpina/etc...
*SIS...
*Symphony...
*TI (Texas Instruments)...
*UMC...
*Unresearched:...
*VIA...
**VT82C570M    Apollo Master, Green Pentium/P54C             <06/22/95
***Info:
The VT82C570M Apollo Master  is a high performance, cost-effective and
energy efficient  chip set for  the implementation of  PCI/ISA desktop
and   notebook  personal   computer  systems   based  on   the  64-bit
P54C/Pentium/K5/M1 super-scalar processors. Either  3.3v or 5v CPU and
cache interface is supported up  to 66Mhz CPU external bus speed (with
CPU internal speed up to 150Mhz  and above). In either case, DRAM, PCI
and ISA bus runs at 5v voltage level.

The VT82C570M  chip set consists  of the VT82C575M  system controller,
the  VT82C576M   PCI  bus  controller  with   integrated  master  mode
Enhanced-IDE  controller,  and two  instances  of  the VT82C577M  data
buffers. The CPU bus is  minimally loaded with only the CPU, secondary
cache and the chip set. The VT82C577M data buffers isolate the CPU bus
from the DRAM, PCI and ISA bus so that CPU and cache operation may run
reliably at the high  frequencies demanded by today's processors.  The
chip set  also interfaces directly with the  VT82C416 integrated clock
generator, real time clock with  extended CMOS (128 byte) and keyboard
controller  with PS2  mouse  support.  A complete  main  board can  be
implemented  with only  ten TTLs.  Please refer  to Figure  1  for the
system block diagram.

The  VT82C570M supports eight  banks of  DRAMs up  to 512MB.  The DRAM
controller  supports  Standard  Page  Mode DRAM,  EDO-DRAM  and  Burst
EDO-DRAM in  a flexible mixed/match  manner.  The eight banks  of DRAM
are   grouped  into   four  pairs   with  an   arbitrary   mixture  of
256K/512K/1M/2M/4M/8M/16MxN  DRAMs. Zero,  one  or both  banks may  be
populated in each pair with either 32bit or 64bit data width.

The secondary (L2)  cache is based on Burst  Synchronous (Pipelined or
non-pipelined) SRAM,  asynchronous SRAM or cache module  from 128KB to
2MB. For burst  synchronous SRAMs, 3-1-1-1 timing can  be achieved for
both read and write transactions at 66Mhz. For standard SRAMs, 3-2-2-2
and  4-2-2-2 timing  can be  achieved for  interleaved read  and write
transactions at 66Mhz. Four levels  of CPU/cache to DRAM write buffers
with concurrent  write-back capability  are included in  the VT82C577M
data  buffer  chips  to  speed  up  the  cache  read  and  write  miss
cycles. For primary  cache fill cycles that result  in secondary cache
misses, the primary and secondary caches are filled up concurrently to
further enhance the performance.

***Configurations:...
***Features:...
**VT82C580VP   Apollo VP,  Pentium/M1/K5 PCI/ISA System      <02/15/96...
**VT82C580VPX  Apollo VPX, VPX/97, Pentium with 66/75MHz Bus <01/09/97...
**VT82C590     Apollo VP2, VP2/97, Single-Chip Pentium 66MHz <01/10/97...
**VT82C597/AT  Apollo VP3, Single-Chip for Pentium with AGP  <10/03/97...
**VT82C598MVP  Apollo MVP3,Single-Chip 66/75/83/100MHz & AGP <09/22/97...
**VT8501       Apollo MVP4,Single-Chip 66-100MHz & AGP       <11/04/98...
**VT82C680     Apollo P6, Pentium-Pro Chip Set               <08/30/96...
**Support chips:
**VT82C505     Pentium/486 VL to PCI Bridge                  <05/30/94...
**VT82C586/A/B PCI Integrated Peripheral Controller          <10/13/96...
**VT82C596/A   Mobile PCI Integrated Peripheral Controller   <11/05/97...
**VT82C686A/B  PCI Super-I/O Integrated Peripheral Ctrl.     <02/10/98...
**Later P-Pro/II/III/Celeron...
**Later AMD...
**Other...
*VLSI...
*Western Digital...
*Winbond...
*ZyMOS...
*General Sources:...