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**82495DX/490DX DX CPU-Cache Chip Set                           <Sep91
***Notes:...
***Info:...
***Configurations:...
***Features:...
**82495XP/490XP Cache Controller / Cache RAM (for i860)       06/05/91
***Notes:...
***Info:...
***Features:
o   Two-Way, Set Associative, Secondary Cache for i860 XP 
    Microprocessor
o   50 MHz "No Glue" Interface with CPU
o   Configurable
    - Cache Size 256 or 512 Kbytes
    - Line Width 32, 64 or 128 Bytes
    - Memory Bus Width 64 or 128 Bits
o   Dual-Ported Structure Permits Simultaneous Operations on CPU and
    Memory Buses
o   Efficient MRU Way Prediction
    - Zero Wait States on MRU Hit
    - One Walt State on MRU Miss
o   Dynamically Selectable Update Policies
    - Write-Through
    - Write-Once
    - Write-Back
o   MESI Cache Consistency Protocol
o   Hardware Cache Snooping
o   Maintains Consistency with Primary Cache via Inclusion Principle
o   Flexible User-Implemented Memory Interface Enables Wide Range of
    Product Differentiation
    - Clocked or Strobed
    - Synchronous or Asynchronous
    - Plpelining
    - Memory Bus Protocol
o   82495XP Cache Controller Available in 208-Lead Ceramic Pin Grid 
    Array Package
o   82490XP Cache RAM Available in 84-Lead Plastic Quad Flatpack 
    Package

**82496/491     Cache Controller / Cache RAM (for P5 Pentium) 03/22/93...
**82497/492   Cache Controller / Cache RAM (for P54 Pentium)    <Nov94...
**82498/493   Cache Controller / Cache RAM (for P54 Pentium)    <Nov94...
**
**Later chipsets (basic spec):
**440 series:...
**450NX  (?)            06/29/98:...
**?????  (Profusion)    c:99...
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*VIA...
**SL9352   80386DX System and Memory Controller              <06/12/90
***Info:
VIA’s  System and  Memory Controller  SL9352,  has the  logic for  the
System Control, Memory Control, Data  Control and chip select for some
of  the  peripherals  used  in  an  AT system.  The  device  is  fully
configurable via software. No  external hardware jumpers are needed to
utilize its features.  Default values are provided to  boot any system
configuration. On reset, BIOS routines are used to program the device,
transparent to the user, to utilize its special features.

Four configuration  registers in the System Control  Logic control the
AT bus and peripheral bus operations. Synchronous and asynchronous bus
operations are  supported. In synchronous  mode, bus clock  is derived
from the processor's CLK2. In asynchronous mode, it is derived from an
independent external bus clock pin.

Support for page mode  and non-page mode operation with non-interleave
or word /multi-page interleave, along with programmable memory timing,
allow the  system designer to  get maximum performance for  the chosen
DRAMs. High  drive for RAS, CAS,  memory address, and  write lines are
provided  to connect  SL9352 directly  to  a large  DRAM memory  array
without  external buffering.  In addition,  CAS for  all the  banks in
non-interleave and  2-way interleave  are provided to  reduce external
gates.

Shadowing  features are  supported  in 16K  granularity  from 640K  to
1M. Remap  options allow shadowing of eight  different combinations of
tap of memory, Local ROM, and Video ROM to 640K to 1M region.

VlA's System  and Memory Controller, SL9352,  can be used  with two of
VIA's  SL9020   Data  Controllers,   or  with  discrete   latches  and
buffers. Data direction and enable signals for the data controller are
provided for both modes of operation.

SL9352  provides  decoding  for  the  Real  Time  Clock  and  Keyboard
Controller, thus avoiding external decoding gates. In addition, Port B
logic, PS/Z Compatible Port 92 for fast reset, and A20GATE provide the
necessary logic support for a one-chip solution.

***Versions:...
***Features:...
**SLXXXX   Other chips...
**
**VT82C470     "Jupiter", Chip Set (w/o cache) 386 [no datasheet]    ?
**VT82C475     "Jupiter", Chip Set (w/cache) 386   [no datasheet]    ?
**VT82C486/2/3 "GMC chipset"            [no datasheet, some info]    ?...
**VT82C495/480 "Venus" Chip Set                    [no datasheet]    ?
**VT82C495/491 ? EISA Chip Set          [no datasheet, some info]  <93...
**VT82C496G    Pluto, Green PC 80486 PCI/VL/ISA System       <05/30/94...
**VT82C530MV   3.3V Pentium chipset [no datasheet, some info]<05/30/94...
**VT82C570M    Apollo Master, Green Pentium/P54C             <06/22/95...
**VT82C580VP   Apollo VP,  Pentium/M1/K5 PCI/ISA System      <02/15/96...
**VT82C580VPX  Apollo VPX, VPX/97, Pentium with 66/75MHz Bus <01/09/97...
**VT82C590     Apollo VP2, VP2/97, Single-Chip Pentium 66MHz <01/10/97...
**VT82C597/AT  Apollo VP3, Single-Chip for Pentium with AGP  <10/03/97...
**VT82C598MVP  Apollo MVP3,Single-Chip 66/75/83/100MHz & AGP <09/22/97...
**VT8501       Apollo MVP4,Single-Chip 66-100MHz & AGP       <11/04/98...
**VT82C680     Apollo P6, Pentium-Pro Chip Set               <08/30/96...
**Support chips:
**VT82C505     Pentium/486 VL to PCI Bridge                  <05/30/94...
**VT82C586/A/B PCI Integrated Peripheral Controller          <10/13/96...
**VT82C596/A   Mobile PCI Integrated Peripheral Controller   <11/05/97...
**VT82C686A/B  PCI Super-I/O Integrated Peripheral Ctrl.     <02/10/98...
**Later P-Pro/II/III/Celeron...
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