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**82495XP/490XP Cache Controller / Cache RAM (for i860)       06/05/91
***Notes:...
***Info:...
***Features:...
**82496/491     Cache Controller / Cache RAM (for P5 Pentium) 03/22/93...
**82497/492   Cache Controller / Cache RAM (for P54 Pentium)    <Nov94...
**82498/493   Cache Controller / Cache RAM (for P54 Pentium)    <Nov94...
**
**Later chipsets (basic spec):
**440 series:...
**450NX  (?)            06/29/98:...
**?????  (Profusion)    c:99...
**800 series...
*Headland/G2...
*HMC (Hulon Microelectronics)...
*Logicstar...
*Motorola...
*OPTi...
*PC CHIPS/Amptron/Atrend/ECS/Elpina/etc...
*SIS...
**5596/5513      (Genesis) Pentium PCI Chipset               <03/26/96
***Info:...
***Configurations:...
***Features:
o   Supports Intel Pentium CPU and other compatible CPU at 
    66/60/50MHz (external clock speed)
o   Supports VGA Shared Memory Architecture
    - Direct Memory Accesses
    - Shared Memory Area 0.5M, 1M, 1.5M, 2M, 2.5M, 3M, 3.5M, 4M.
    - Built-in 2-Priority Scheme.
o   Supports the Pipelined Address Mode of Pentium CPU.
o   Integrated Second Level (L2) Cache Controller
    - Write Through and Write Back Cache Modes
    - 8 bits or 7 bits Tag with Direct Mapped Cache Organization
    - Supports Pipelined Burst SRAM.
    - Supports 256 KBytes to 1 MBytes Cache Sizes.
    - Cache Read/Write Cycle of 3-1-1-1 Pipelined Burst SRAM at 66 
      Mhz and 3-1-1-1-1-1-1-1 at back to back read cycle.
o   Integrated DRAM Controller
    - Supports 4 RAS lines, the memory size is from 4MBytes up to 
      512Mbytes.
    - Supports 256K/512K/1M/2M/4M/16M x N 70ns FP/EDO DRAM
    - Supports 4K Refresh DRAM
    - Supports 3V or 5V DRAM.
    - Supports Symmetrical and Asymmetrical DRAM.
    - Supports 32 bits/64 bits mixed mode configuration
    - Supports Concurrent Write Back
    - Table-free DRAM Configuration, Auto-detect DRAM size, Bank 
      Density, Single/Double sided DRAM, EDO/ FP DRAM for each bank
    - Supports CAS before RAS "Intelligent Refresh"
    - Supports Relocation of System Management Memory
    - Programmable CAS# Driving Current
    - Fully Configurable for the Characteristic of Shadow RAM (640 
      KByte to 1 Mbyte)
o   Supports EDO/FP 5/6-2-2-2/-3-3-3 Burst Read Cycles
o   Two Programmable Non-Cacheable Regions
o   Option to Disable Local Memory in Non-Cacheable Regions
o   Shadow RAM in Increments of 16 KBytes
o   Supports SMM Mode of CPU.
o   Supports CPU Stop Clock.
o   Supports Break Switch.
o   Provides High Performance PCI Arbiter.
    - Supports 4 PCI Master.
    - Supports Rotating Priority Mechanism.
    - Hidden Arbitration Scheme Minimizes Arbitration Overhead.
    - Supports Concurrency between CPU to Memory and PCI to PCI.
o   Integrated PCI Bridge
    - Supports Asynchronous PCI Clock.
    - Translates the CPU Cycles into the PCI Bus Cycles
    - Provides CPU-to-PCI Read Assembly and Write Disassembly 
      Mechanism
    - Translates Sequential CPU-to-PCI Memory Write Cycles into PCI 
      Burst Cycles.
    - Zero Wait State Burst Cycles.
    - Supports Advance Snooping for PCI Master Bursting.
    - Maximum PCI Burst Transfer from 256 Bytes to 4 KBytes.
o   388-Pin BGA Package.
o   0.5μm CMOS Technology.

**5597/5598      (Jedi)    Pentium PCI/ISA Chipset           <04/15/97...
**530/5595       (Sinbad) Host, PCI, 3D Graphics & Mem. Ctrl.<11/10/98...
**540            (Spartan) Super7 2D/3D Ultra-AGP Single C.S.<11/30/99...
**55x            SoC (System-on-chip)                        <03/14/02...
**
**Support chips:
**85C206     Integrated Peripheral Controller [no datasheet]         ?...
**5595       Pentium PCI System I/O                          <12/24/97...
**950        LPC I/O                                         <07/16/99...
**Other:...
**PII/III/Pro...
**Athlon etc...
*Symphony...
*TI (Texas Instruments)...
*UMC...
*Unresearched:...
*VIA...
**SL9XXX   FlexSet family General information
The SL9XXX series seems to have  been designed to work with the 80286,
80386SX and 80386DX, and is  possibly compatible with the 80486. What-
ever CPU used, the chipset  contains the following chips, known as the
"Core AT Logic chips":

SL9011 System  Controller
SL9020 Data Controller (2x for 32bit 386DX)
SL9025 Address Controller
SL9030 Integrated Peripheral Controller

The memory  controller is then selected  based on the  CPU. It appears
that the lineup originally consisted  of the following chips, known as
"Personalized AT Logic":
SL9151 Page Interleave Memory      (80286)
SL9250 Memory Controller           (80386SX)
SL9350 Page Mode Memory Controller (80386DX)

Later updates were:
SL9251   Page Interleave Memory Controller (80386SX)
SL9351   Page Interleave Memory Controller (80386DX)

Further updates were:
SL9252   System and Memory Controller (80386SX)
SL9352   System and Memory Controller (80386DX)

As far  as i can  tell, these chips  only require the addition  of the
SL9020, or  2x in  the case  of the SL9352.  The datasheets  are quite
terse.

These parts and the whole design of the datasheets are very similar to
the chipsets released by Logicstar. I, however, cannot find any record
of a link between the companies. See *Logicstar for details.

**SL9011   System Controller (80286/80386SX/DX, 16/20/25MHz)    <Jan90...
**SL9020   Data Controller                                      <Jan90...
**SL9025   Address Controller                                   <Jan90...
**SL9030   Integrated Peripheral Controller                     <Jan90...
**SL9090/A Universal PC/AT Clock Chip                           <oct88...
**SL9095   Power  Management Unit                                    ?...
**SL9151   80286 Page Interleave Memory Controller (16-25MHz)        ?...
**SL9250   80386SX Page Mode Memory Controller (16/20MHz 8MB)        ?...
**SL9251   80386SX Page Interleave Memory Controller         <04/13/90...
**SL9252   80386SX System and Memory Controller              <06/12/90...
**SL9350   80386DX Page Mode Memory Controller (16-25MHz 16MB)       ?...
**SL9351   80386DX Page Interleave Memory Controller (33MHz)         ?...
**SL9352   80386DX System and Memory Controller              <06/12/90...
**SLXXXX   Other chips...
**
**VT82C470     "Jupiter", Chip Set (w/o cache) 386 [no datasheet]    ?
**VT82C475     "Jupiter", Chip Set (w/cache) 386   [no datasheet]    ?
**VT82C486/2/3 "GMC chipset"            [no datasheet, some info]    ?...
**VT82C495/480 "Venus" Chip Set                    [no datasheet]    ?
**VT82C495/491 ? EISA Chip Set          [no datasheet, some info]  <93...
**VT82C496G    Pluto, Green PC 80486 PCI/VL/ISA System       <05/30/94...
**VT82C530MV   3.3V Pentium chipset [no datasheet, some info]<05/30/94...
**VT82C570M    Apollo Master, Green Pentium/P54C             <06/22/95...
**VT82C580VP   Apollo VP,  Pentium/M1/K5 PCI/ISA System      <02/15/96...
**VT82C580VPX  Apollo VPX, VPX/97, Pentium with 66/75MHz Bus <01/09/97...
**VT82C590     Apollo VP2, VP2/97, Single-Chip Pentium 66MHz <01/10/97...
**VT82C597/AT  Apollo VP3, Single-Chip for Pentium with AGP  <10/03/97...
**VT82C598MVP  Apollo MVP3,Single-Chip 66/75/83/100MHz & AGP <09/22/97...
**VT8501       Apollo MVP4,Single-Chip 66-100MHz & AGP       <11/04/98...
**VT82C680     Apollo P6, Pentium-Pro Chip Set               <08/30/96...
**Support chips:
**VT82C505     Pentium/486 VL to PCI Bridge                  <05/30/94...
**VT82C586/A/B PCI Integrated Peripheral Controller          <10/13/96...
**VT82C596/A   Mobile PCI Integrated Peripheral Controller   <11/05/97...
**VT82C686A/B  PCI Super-I/O Integrated Peripheral Ctrl.     <02/10/98...
**Later P-Pro/II/III/Celeron...
**Later AMD...
**Other...
*VLSI...
*Western Digital...
*Winbond...
*ZyMOS...
*General Sources:...

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