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**82498/493   Cache Controller / Cache RAM (for P54 Pentium)    <Nov94
***Notes:...
***Info:...
***Configurations:...
***Features:...
**
**Later chipsets (basic spec):
**440 series:...
**450NX  (?)            06/29/98:...
**?????  (Profusion)    c:99...
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**UM82C3xx     Twinstar & UM82C336F/N & UM82C39x [no datasheet]      ?
***Notes:...
**UM82C380     386 HEAT PC/AT Chip Set                             <91...
**UM82C480     386/486 PC Chip Set                                 c91...
**UM82C493/491 ??????????????? [no datasheet]                        ?...
**UM8498/8496  486 VL Chipset  "Super Energy Star Green"[no dsheet]c94...
**UM8881/8886  HB4 PCI Chipset "Super Energy Star Green"[no dsheet]c94...
**UM8890       Pentium chipset [no datasheet]                        ?...
**
**Support Chips:
**UM82152      Cache Controller (AUStek A38152 clone)              <91...
**UM82C852     Multi I/O For XT                                    <91...
**UM82C206     Integrated Peripheral Controller                    <91...
**UM82c45x     Serial/Parallel chips                                 ?
***Notes:...
**Other chips:...
*Unresearched:...
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*Western Digital...
**WD76C30x   Perip. Ctrl, Interrupt Multiplex, and Clock Gen <11/18/91
***Notes:...
***Info:...
***Versions:...
***Features:
o   Two fully programmable and independent serial I/O ports 
    configurable as PC/AT compatible (WD16C452) or PS/2 
    compatible (WD16C552)
    - Loopback controls for communications link fault isolation for 
      each ACE
    - Line break generation and detection for each ACE
    - Complete status reporting capabilities
    - Generation and stripping of serial asynchronous data control 
      bits (start, stop, parity)
    - Programmable baud rate generator and MODEM control signals for 
      each port
    - Programmable baud rate generator input clock
    - Optional 16 byte FIFO buffers on both transmit and receive of 
      each port for CPU relief during high speed data transfer
    - Programmable FIFO threshold levels of 1 , 4, 8, or 14 bytes on 
      each port
o   Parallel port configurable as a fully Centronics or PS/2 
    compatible, bidirectional parallel port
o   Independently programmable parallel port
o   Interrupt multiplexing logic
    - Selectable multiplexing logic for connecting PC/AT interrupt 
      request lines to the WD76C10 single chip AT controller
o   Clock generation circuitry
    - 80287 coprocessor clock generation
    - WD76C10 and floppy controller clock generation
    - 8042 keyboard clock generation
o   Built-in testability features
o   Hardware or software controllable sleep mode
o   CMOS implementation for high speed and low power requirements 
o   Pulse extension on IRQ inputs
o   84-pin PLCC and PQFP packages

**WD7615     Desktop Buffer Manager                          <04/15/92...
**WD7625     Desktop Buffer Manager                          <10/01/92...
**WD8120LV   Super I/O [no datasheet]                                ?
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