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*AMD . . . . . . . [no datasheets, some info]...
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*Intel...
**82495XP/490XP Cache Controller / Cache RAM (for i860)       06/05/91
***Notes:...
***Info:
The Intel 82495XP cache controller and 82490XP cache RAM, when coupled
with a user-implemented memory  bus controller, provide a second-level
cache  subsystem  that eliminates  the  memory  latency and  bandwidth
bottleneck for  a wide  range of multiprocessor  systems based  on the
i860 XP  microprocessor. The CPU  interface is optimized to  serve the
i860  XP microprocessor  with zero  wait  states at  up to  50 MHz.  A
secondary cache  built from the  82495XP and 82490XP isolates  the CPU
from  the memory subsystem;  the memory  can run  slower and  follow a
different protocol than the i860 XP microprocessor.
         
***Features:...
**82496/491     Cache Controller / Cache RAM (for P5 Pentium) 03/22/93...
**82497/492   Cache Controller / Cache RAM (for P54 Pentium)    <Nov94...
**82498/493   Cache Controller / Cache RAM (for P54 Pentium)    <Nov94...
**
**Later chipsets (basic spec):
**440 series:...
**450NX  (?)            06/29/98:...
**?????  (Profusion)    c:99...
**800 series...
*Headland/G2...
*HMC (Hulon Microelectronics)...
*Logicstar...
*Motorola...
*OPTi...
*PC CHIPS/Amptron/Atrend/ECS/Elpina/etc...
*SIS...
**540            (Spartan) Super7 2D/3D Ultra-AGP Single C.S.<11/30/99
***Info:...
***Configurations...
***Features:...
**55x            SoC (System-on-chip)                        <03/14/02...
**
**Support chips:
**85C206     Integrated Peripheral Controller [no datasheet]         ?...
**5595       Pentium PCI System I/O                          <12/24/97...
**950        LPC I/O                                         <07/16/99...
**Other:...
**PII/III/Pro...
**Athlon etc...
*Symphony...
*TI (Texas Instruments)...
*UMC...
**UM82C852     Multi I/O For XT                                    <91
***Info:...
***Versions:...
***Features:
o   Supports game port
o   Supports 2nd serial port
o   Centronics printer interface
o   Independent control of transmit, receive, line status and data set 
    interrupts
o   Individual modem control signals
o   Programmable serial interface characteristics:
    — 5, 6, 7 , or 8 bit characters
    — Even, odd or no-parity bit generation and detection
    — 1, 1-1/2, or 2 stop bit generation
o   Milliseconds through month counters for real time clock 56 bits of
    RAM 
    with comparator for comparing the real time counter to the RAM 
    data
o   POWER DOWN input that disables all inputs and outputs
o   Disables the chip from the reset of the system for standby low 
    power operation by use of a POWER DOWN input
o   32,768 Hz crystal for real time clock
o   Four-year calendar (no leap year)
o   24-hour clock

**UM82C206     Integrated Peripheral Controller                    <91...
**UM82c45x     Serial/Parallel chips                                 ?...
**Other chips:...
*Unresearched:...
*VIA...
*VLSI...
*Western Digital...
*Winbond...
*ZyMOS...
*General Sources:...