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**M???? Genie, Quad Pentium [no datasheet, some info] c95
***Notes:
It looks like this was never released, very little info, the 4-CPU
support of the Pentium is inconsistent with the Intel SMP
architecture.
Mentioned in:
EDN, Electrical Design News - Volume 40, Issues 13-16 - p24 (c1995)
"The Genie chip set suits multiprocessor applications..."
http://www.os2forum.or.at/english/info/os2hardwareinfo/pci_chips.html
"
3) The Genie Chipset (Acer Labs: 10B9/4281) (8/27/95)
This is a chipset by Acer Laboratories Inc. (ALI) which is intended
for use in multiprocessing systems. Specifically, the chipset will
support up to four P54C, P55C, Cyrix M1 or AMD K5 processors, though I
don't know if you can "mix and match" the CPUs (though I doubt
it). I've had no reports of success or failure with boards which use
this chipset. "
**M1451/49 Aladdin (Pentium) [no datasheet] ?...
**M1511/12/13 Aladdin II (Pentium) [no datasheet, some info] >Apr95...
**M1521/23 Aladdin III 50-66MHz <Nov96...
**M1531/33/43 Aladdin IV & IV+ 50-83.3MHz <05/28/97...
**M1541/42/33/43 Aladdin V & V+ 50-100MHz ?...
**M1561/43/35D Aladdin 7 ArtX [no datasheet, some info] 11/08/99...
**M6117 386SX Single Chip PC <97...
**
**Support Chips:
**M1535/D South Bridge ?...
**
**May not exist:...
**Later Chipsets:...
**Other:...
*AMD . . . . . . . [no datasheets, some info]...
*Chips & Technologies...
*Contaq . . . . . [no datasheets, some info]...
*Efar Microsystems [no datasheets, some info]...
*ETEQ...
*Faraday...
*Forex . . . . . . [List only, no datasheets found]...
*Intel...
**82495XP/490XP Cache Controller / Cache RAM (for i860) 06/05/91
***Notes:...
***Info:...
***Features:
o Two-Way, Set Associative, Secondary Cache for i860 XP
Microprocessor
o 50 MHz "No Glue" Interface with CPU
o Configurable
- Cache Size 256 or 512 Kbytes
- Line Width 32, 64 or 128 Bytes
- Memory Bus Width 64 or 128 Bits
o Dual-Ported Structure Permits Simultaneous Operations on CPU and
Memory Buses
o Efficient MRU Way Prediction
- Zero Wait States on MRU Hit
- One Walt State on MRU Miss
o Dynamically Selectable Update Policies
- Write-Through
- Write-Once
- Write-Back
o MESI Cache Consistency Protocol
o Hardware Cache Snooping
o Maintains Consistency with Primary Cache via Inclusion Principle
o Flexible User-Implemented Memory Interface Enables Wide Range of
Product Differentiation
- Clocked or Strobed
- Synchronous or Asynchronous
- Plpelining
- Memory Bus Protocol
o 82495XP Cache Controller Available in 208-Lead Ceramic Pin Grid
Array Package
o 82490XP Cache RAM Available in 84-Lead Plastic Quad Flatpack
Package
**82496/491 Cache Controller / Cache RAM (for P5 Pentium) 03/22/93...
**82497/492 Cache Controller / Cache RAM (for P54 Pentium) <Nov94...
**82498/493 Cache Controller / Cache RAM (for P54 Pentium) <Nov94...
**
**Later chipsets (basic spec):
**440 series:...
**450NX (?) 06/29/98:...
**????? (Profusion) c:99...
**800 series...
*Headland/G2...
*HMC (Hulon Microelectronics)...
*Logicstar...
*Motorola...
*OPTi...
*PC CHIPS/Amptron/Atrend/ECS/Elpina/etc...
*SIS...
*Symphony...
*TI (Texas Instruments)...
*UMC...
**UM82152 Cache Controller (AUStek A38152 clone) <91
***Info:...
***Versions:...
***Features:...
**UM82C852 Multi I/O For XT <91...
**UM82C206 Integrated Peripheral Controller <91...
**UM82c45x Serial/Parallel chips ?...
**Other chips:...
*Unresearched:...
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