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*AMD . . . . . . . [no datasheets, some info]...
*Chips & Technologies...
*Contaq . . . . . [no datasheets, some info]...
*Efar Microsystems [no datasheets, some info]...
*ETEQ...
*Faraday...
*Forex . . . . . . [List only, no datasheets found]...
*Intel...
**800 series
***810 (Whitney) 04/26/99...
***810L (Whitney) 04/26/99...
***810-DC100 (Whitney) 04/26/99...
***810e (Whitney) 09/27/99...
***810e2 (Whitney) 01/03/01...
***815 (Solano) 06/19/00...
***815e (Solano-2) 06/19/00...
***815em (Solano-?) 10/23/00...
***815ep (Solano-3) c:Nov'00...
***815p (Solano-3) c:Mar'01...
***815g (Solano-3) c:Sep'01...
***815eg (Solano-3) c:Sep'01...
***820 (Camino) 11/15/99...
***820e (Camino-2) 06/05/00...
***830M (Almador) 07/30/01...
***830MP (Almador) 07/30/01...
***830MG (Almador) 07/30/01...
***840 (Carmel) 10/25/99...
***845 (Brookdale) 09/10/01...
***845MP (Brookdale-M) 03/04/02...
***845MZ (Brookdale-M) 03/04/02...
***845E (Brookdale-E) 05/20/02...
***845G (Brookdale-G) 05/20/02...
***845GL (Brookdale-GL) 05/20/02...
***845GE (Brookdale-GE) 10/07/02...
***845PE (Brookdale-PE) 10/07/02...
***845GV (Brookdale-GV) 10/07/02...
***848P (Breeds Hill) c:Aug'03...
***850 (Tehama) 11/20/00...
***850E (Tehama-E) 05/06/02...
***852GM (Montara-GM) 01/14/03...
***852GMV (Montara-GM) ???...
***852PM (Montara-GM) 06/11/03...
***852GME (Montara-GM) 06/11/03...
***854 (?) 04/11/05...
***855GM (Montara-GM) 03/12/03...
***855GME (Montara-GM) 03/12/03...
***855PM (Odem) 03/12/03...
***860 (Colusa) 05/21/01...
***865G (Springdale) 05/21/03...
***865PE (Springdale-PE) 05/21/03...
***865P (Springdale-P) 05/21/03...
***865GV (Springdale-GV) c:Sep'03...
***875P (Canterwood) 04/14/03...
*Headland/G2...
*HMC (Hulon Microelectronics)...
*Logicstar...
*Motorola...
*OPTi...
*PC CHIPS/Amptron/Atrend/ECS/Elpina/etc...
*SIS...
*Symphony...
**SL82C460 'Haydn II' 80486 chipset [no datasheet] c:Jun91
***Notes:...
***Configurations:...
**SL82C470 'Mozart' 486/386 EISA chipset c:Dec91...
**SL82C490 'Wagner' 486? [no datasheet] ?
***Notes:...
**SL82C550 'Rossini' Pentium [no datasheet] c:95...
**
**Support Chips:
**SL82C365 Cache Controller (for 386DX/SX) c:91...
**SL82C465 Cache Controller (for 486/386DX/SX) c:91...
*TI (Texas Instruments)...
*UMC...
*Unresearched:...
*VIA...
**VT82C680 Apollo P6, Pentium-Pro Chip Set <08/30/96
***Notes:...
***Info:...
***Configurations:...
***Features:
o High Integration
- VT82C685 system controller
- VT82C687 data buffer
- VT82C586 PCI to ISA bridge
- Six TTLs for a complete main board implementation
o Flexible CPU Interface
- 64 bit Pentium-Pro CPU interface
- CPU external bus speed up to 66 MHz
- Supports Pentium-Pro CPU multi-phase bus protocol for split
transactions
- Supports four level deep in-order-queue and deferred transaction
- Supports APIC multiprocessor protocol
- GTL+TM bus driver and receiver compatible with Intel
specification
o Fast DRAM Controller
- Sixteen level (quadwords) of CPU to DRAM write buffers
- Sixteen level (quadwords) of DRAM to CPU read buffers
- Fast Page Mode/EDO/Burst EDO/Synchronous-DRAM support in a mixed
combination
- Mixed 1M/2M/4M/8M/16MxN DRAMs
- Supports 2-way bank-interleaving of 16 MB SDRAM
- Supports 2-way and 4-way bank-interleaving of 64 MB SDRAM
- 6 banks up to 1 GB DRAMs
- Flexible row and column addresses
- Optional bank-by-bank ECC and parity generation, detection, and
correction capability
- ECC with 1 bit error correction and multi-bit error detection
capability
- 3.3v and 5v DRAM without external buffers
- Burst read and write operation
- 5-1-1-1-1-1-1-1 back-to-back Burst EDO and Synchronous DRAM
transfer at 66 MHz
- 532 MB/s peak transfer rate for Burst EDO and Synchronous DRAMs
at 66 MHz
- 266 MB/s peak transfer rate for EDO DRAMs at 66 MHz
- BIOS shadow at 16 kB increment
- System management memory remapping
- Decoupled and burst DRAM refresh with staggered RAS timing
- Programmable refresh rate, CAS-before-RAS refresh and refresh
on populated banks only
o Intelligent PCI Bus Controller
- 32 bit 3.3/5v PCI interface
- Synchronous divide-by-two PCI bus interface
- PCI master snoop ahead and snoop filtering
- Concurrent PCI master/CPU/IDE operations
- Synchronous Bus to CPU clock with divide-by-two from the CPU
clock
- Automatic detection of data streaming burst cycles from CPU to
the PCI bus
- Sixteen levels (double-words) of CPU to PCI posted write buffers
- Byte merging in the write buffers to reduce the number of PCI
cycles and to create further PCI bursting possibilities
- Zero wait state PCI master and slave burst transfer rate
- PCI to system memory data streaming up to 132 MByte/sec
- Sixteen levels (double-words) of post write buffers from PCI
masters to DRAM
- Sixteen levels (double-words) of prefetch buffers from DRAM for
access by PCI masters
- Enhanced PCI command optimization (MRL, MRM, MWI, etc.)
- Complete steerable PCI interrupts
- Supports CPU write-back forward to PCI master read to minimize
PCI read latency
- Supports CPU write-back merged with PCI master post-write to
minimize DRAM utilization
- Provides transaction timer to fairly arbitrate between PCI
masters
- Supports five PCI masters in addition to PCI-ISA/IDE/USB bridge
- PCI-2.1 compliant
o Enhanced Master Mode PCI IDE Controller with Extension to
UltraDMA-33
- Dual channel master mode PCI supporting four Enhanced IDE
devices
- Transfer rate up to 22 MB/sec to cover PIO mode 4 and multi-word
DMA mode 2 drives and beyond
- Extension to UltraDMA-33 interface for up to 33 MB/sec transfer
rate
- Sixteen levels (doublewords) of prefetch and write buffers
- Interlaced commands between two channels
- Bus master programming interface for SFF-8038 rev.1.0 and
Windows-95 compliant
- Full scatter and gather capability
- Support ATAPI compliant devices
- Support PCI native and ATA compatibility modes
- Complete software driver support
o Universal Serial Bus Controller
- USB v.1.0 and Intel Universal HCI v.1.1 compatible
- Eighteen level (doubleword) of data FIFOs with full scatter
and gather capabilities
- Root hub and two function ports with integrated physical
layer transceivers
- Legacy keyboard and PS2 mouse support
o Plug and Play Controller
- Dual interrupt and DMA signal steering with plug and play
control
- Microsoft Windows 95TM and plug and play BIOS compliant
o Sophisticated Power Management and OnNow/ACPI Unit
- Normal, doze, sleep, suspend and conserve modes
- System event monitoring with two event classes
- Two general purpose timers
- Sixteen general purpose output ports
- Seven external event input ports with programmable SMI condition
- Primary and secondary interrupt differentiation for individual
channels
- Clock throttling control
- Multiple internal and external SMI sources for flexible power
management models
- APM 1.2 compliant models
- Extension to OnNow and ACPI (Advanced Configuration and Power
Interface) support
o PCI to ISA Bridge
- Integrated 82C206 peripheral controller
- Integrated keyboard controller with PS2 mouse supports
- Integrated DS12885 style real time clock with extended 128 Byte
CMOS RAM
- Integrated USB controller with root hub and two function ports
- Integrated master mode enhanced IDE controller with enhanced
PCI bus commands
- PCI-2.1 compliant with delay transaction
- Four double-word line buffer between PCI and ISA bus
- Supports type F DMA transfers
- Fast reset and Gate A20 operation
- Edge trigger or level sensitive interrupt
- Flash EPROM, 2 MB EPROM and combined BIOS support
o Built-in Nand-tree pin scan test capability
o 0.5um mixed voltage, high speed and low power CMOS process
o 208 pin PQFP for VT82C685
o 208 pin PQFP for VT82C586
o 208 pin PQFP for VT82C687
**Support chips:
**VT82C505 Pentium/486 VL to PCI Bridge <05/30/94...
**VT82C586/A/B PCI Integrated Peripheral Controller <10/13/96...
**VT82C596/A Mobile PCI Integrated Peripheral Controller <11/05/97...
**VT82C686A/B PCI Super-I/O Integrated Peripheral Ctrl. <02/10/98...
**Later P-Pro/II/III/Celeron...
**Later AMD...
**Other...
*VLSI...
*Western Digital...
*Winbond...
*ZyMOS...
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