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**82498/493   Cache Controller / Cache RAM (for P54 Pentium)    <Nov94
***Notes:...
***Info:...
***Configurations:...
***Features:...
**
**Later chipsets (basic spec):
**440 series:
***440FX (Natoma)       05/06/96...
***440LX (Balboa)       08/27/97...
***440BX (Seattle)      c:Apr'98...
***440DX (?)            c:?...
***440EX (?)            c:Apr'98...
***440GX (Marlinespike) 06/29/98...
***440ZX & 440ZX-66 (?) 01/04/99...
***440ZX-M (?)          05/17/99...
***440MX (Banister)     05/17/99...
**450NX  (?)            06/29/98:...
**?????  (Profusion)    c:99...
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**5511/5512/5513 Pentium PCI/ISA                             <06/14/95
***Info:...
***Configurations:...
***Features:
****5511 PCI/ISA Cache Memory Controller (PCMC) 
o   Supports Intel Pentium CPU and other compatible CPU at 66/60/50MHz 
    (external clock speed)
o   Supports Slice MP Protocol
o   Supports the Pipelined Address Mode of Pentium CPU.
o   Integrated Second Level ( L2 ) Cache Controller
    - Write Through and Write Back Cache Modes
    - 8 bits or 7 bits Tag with Direct Mapped Cache Organization
    - Supports Standard, Burst and Pipelined Burst SRAMs.
    - Supports 64 KBytes to 1 MBytes Cache Sizes.
    - Cache Read/Write Cycle of 3-2-2-2 or 4-2-2-2 Using Standard 
      SRAMs at 66 MHz.
    - Cache Read/Write Cycle of 3-1-1-1 Using Burst or Pipelined 
      Burst SRAMs at 66 MHz.
o   Integrated DRAM Controller
    - Supports 4 Banks of SIMMs, the memory size is from 2MBytes up to 
      512Mbytes. (5511 decodes memory space up to 1 Gbytes actually, 
      but limited by current DRAM modules 512Mbytes is the maximum 
      now.)
    - Supports 256K/512K/1M/2M/4M/16M x N 70ns Fast Page Mode and 
      EDO DRAM
    - Supports 3V or 5V DRAM.
    - Supports Symmetrical and Asymmetrical DRAM.
    - Supports Half-Populated (32 bits) Configuration for Bank 0
    - Supports Concurrent Write Back
    - Bank Interleave Mode for 6-2-2-2 Read Cycle
    - Supports FP DRAM 6-3-3-3 Burst Read Cycle.
    - Supports EDO Type DRAM.
    - Supports 6-2-2-2 Burst Read Cycle.
    - Supports X-2-2-2/X-3-3-3 Burst Write Cycle.
    - Supports Read Cycle Power Saving Mode.
    - Table-free DRAM Configuration, Auto-detect DRAM size, Bank 
      Density, Single/Double sided DRAM, EDO/ FP DRAM for each bank
    - Supports CAS before RAS "Intelligent Refresh"
    - Supports Relocation of System Management Memory
    - Optional Parity Checking
    - Programmable CAS# Driving Current
    - Fully Configurable for the Characteristic of Shadow RAM ( 640 
      KByte to 1 MByte)
o   Two Programmable Non-Cacheable Regions
o   Option to Disable Local Memory in Non-Cacheable Regions
o   Shadow RAM in Increments of 16 KBytes
o   Supports SMM Mode of CPU.
o   Supports CPU Stop Clock.
o   Supports Break Switch.
o   Provides High Performance PCI Arbiter.
    - Supports 4 PCI Master.
    - Supports Rotating Priority Mechanism.
    - Hidden Arbitration Scheme Minimizes Arbitration Overhead.
    - Supports Concurrency between CPU to Memory and PCI to PCI.
o   Integrated PCI Bridge
    - Supports Asynchronous PCI Clock.
    - Translates the CPU Cycles into the PCI Bus Cycles
    - Provides CPU-to-PCI Read Assembly and Write Disassembly 
      Mechanism
    - Translates Sequential CPU-to-PCI Memory Write Cycles into PCI 
      Burst Cycles.
    - Zero Wait State Burst Cycles.
    - Provides A Prefetch Mechanism Dedicated for IDE Read.
    - Supports Advance Snooping for PCI Master Bursting.
    - Maximum PCI Burst Transfer from 256 Bytes to 4 KBytes.
o   208-Pin PQFP.
o   0.6μm CMOS Technology.

****5512 PCI Local Data Buffer (PLDB) ...
****5513 PCI System I/O (PSIO)...
**5571           (Trinity) Pentium PCI/ISA Chipset (75MHz)   <12/09/96...
**5581/5582      (Jessie)  Pentium PCI/ISA Chipset (75MHz)   <04/15/97...
**5591/5592/5595 (David)   Pentium PCI A.G.P. Chipset        <01/09/98...
**5596/5513      (Genesis) Pentium PCI Chipset               <03/26/96...
**5597/5598      (Jedi)    Pentium PCI/ISA Chipset           <04/15/97...
**530/5595       (Sinbad) Host, PCI, 3D Graphics & Mem. Ctrl.<11/10/98...
**540            (Spartan) Super7 2D/3D Ultra-AGP Single C.S.<11/30/99...
**55x            SoC (System-on-chip)                        <03/14/02...
**
**Support chips:
**85C206     Integrated Peripheral Controller [no datasheet]         ?...
**5595       Pentium PCI System I/O                          <12/24/97...
**950        LPC I/O                                         <07/16/99...
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