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**82497/492 Cache Controller / Cache RAM (for P54 Pentium) <Nov94
***Notes:...
***Info:
The 82497 Cache Controller and multiple 82492 Cache SRAMs combine with
the Pentium processor (735\90, 810\100) to form a CPU Cache chip set
designed for high performance servers and function-rich desktops. The
high-speed interconnect between the CPU and cache components has been
optimized to provide zero-wait state operation. This CPU Cache chip
set is fully compatible with existing software, and has new data
integrity features for mission critical applications.
The 82497 cache controller implements the MESI write-back protocol for
full multiprocessing support. Dual ported buffers and registers allow
the 82497 to concurrently handle CPU bus, memory bus, and internal
cache operation for maximum performance.
The 82492 is a customized high-performance SRAM that supports 32-,
64-, 128-bit wide memory bus widths, 16-, 32-, and 64-byte line sizes,
and optional sectoring. The data path between the CPU bus and memory
bus is separated by the 82492, allowing the CPU bus to handshake
synchronously, asynchronously, or with a strobed protocol, and
allowing concurrent CPU bus and memory bus operations.
***Configurations:...
***Features:...
**82498/493 Cache Controller / Cache RAM (for P54 Pentium) <Nov94...
**
**Later chipsets (basic spec):
**440 series:...
**450NX (?) 06/29/98:...
**????? (Profusion) c:99...
**800 series...
*Headland/G2...
*HMC (Hulon Microelectronics)...
*Logicstar...
*Motorola...
*OPTi...
**82C381/382 HiD/386 (386DX) c:89
***Info:...
***Configurations:...
***Features:...
**82C391/392 386WB PC/AT Chipset (386DX) <Dec90...
**82C461/462 Notebook PC/AT chipset [no datasheet] ?...
**82c463 SCNB Single Ship Notebook c:92...
**82c465MV/A/B Single-Chip Mixed Voltage Notebook Solution <Oct97...
**82C481?/482? HiP/486 & HiB/486 [no datasheet] Oct89...
**82C491/392 486WB PC/AT Chipset <04/21/91...
**82C493/392 486SXWB <10/21/91...
**82C495SX/392SX LCWB PC/AT chipset [no datasheet] ?...
**82C495SLC DXSLC 386/486 Low Cost Write Back c:92...
**82C495XLC PC/AT Chip Set c:93...
**82c496A/B DXBB PC/AT Chipset <Mar92...
**82C496/7 DXBB PC/AT Chipset (Cached) <01/16/92...
**82C498 DXWB PC/AT chipset [no datasheet] ?...
**82C499 DXSC DX System Controller c:93...
**82C546/547 Python PTM3V c:94...
**82C556/7/8 Viper [no datasheet] ?...
**82C556/7/8N Viper-N Viper Notebook Chipset <05/25/95...
**82C556M/7M/8E Viper-N+ Viper Notebook Chipset c:96...
**82C566/7/8 Viper-Max Chipset Scalable MultiMedia PC Solution ?...
**82C571/572 486/Pentium c:93...
**82C576/7/8 Viper Xpress [no datasheet] ?...
**82C576/8/9 Viper XPress+ [no datasheet, some info] <01/16/97...
**82C596/597 PTMAWB Pentium Adaptive Write-back (Cobra) c:93...
**82C650/1/2 Discovery (Pentium Pro) [no datasheet] ?...
**82C681/2/6/7 386/486WB EISA c:92...
**82C683 386/486AWB EISA [no datasheet] ?...
**82C693/6/7 Pentium uP Write Back Cache EISA c:93...
**82C700 FireStar c:97...
**82C701 FireStar Plus c:97...
**82C750 Vendetta [no datasheet] ?...
**82c801 SCWB2 DX Single Chip Solution c:92...
**82C802 SCWB2 PC/AT Single Chip [no datasheet] ?...
**82C802G/GP System/Power Management Controller (cached) c:93...
**82C895 System/Power Management Controller (cached) c:Sep94...
**82C898 System/Power Management Controller (non-cache)c:Nov94
***Notes:...
***Info:...
***Configurations:...
***Features:
o Processor interface:
- Intel 486SX, DX, DX2, SLe, DX4, P24T, P24D
- AMD 486DX, DX2, DXL, DXL2, Plus
- Cyrix DX, DX2, M7
- CPU frequencies supported 20, 25, 33, 40 and 50MHz
- Auto clock detection
o DRAM interface:
- Up to 128MB main memory support
- Supports 256KB, 1MB, 4MB, and 16MB single- and double-sided SIMM
modules
- Read page-hit timing of 3-2-2-2 at 33MHz
- Supports hidden, slow, and CAS-before-RAS refresh
- Eight RAS lines to support eight banks of DRAM
- Programmable wait states for DRAM reads and writes
- Enhanced DRAM configuration map
- Strong drive on MA lines (12/24mA)
- Supports asymmetric DRAMs
o Power management:
- Support for SMM (System Management Mode) for system power
management implementations
- Programmable power management
- Programmable wake-up events through hardware, software, and
external SMI source
- Multiple level GREEN support (NESTED_GREEN)
- STPCLK# protocol support
- Programmable GREEN event timer
o ISA interface:
- 100% IBM PC/AT ISA compatible
- Integrates DMA, timer, and interrupt controllers
- Optional PS/2 style IRQ1 and IRQ12 latching
o VESA VL interface:
- Conforms to the VESA V2.0 specification
- Optional support for up to two VL masters
o Miscellaneous features:
- Full support for shadow RAM, and write protection for video,
adapter, and system BIOS
- Enhanced arbitration scheme
- Transparent 8042 emulation for fast CPU Reset and Gate A20
generation
o Packaging:
- Higher integration
- Reduced TTL count
- Low-power, high-speed 0.8-micron CMOS technology
- 208-pin PQFP (Plastic Quad Flat Pack)
**
**Support Chips:
**82C601/2 Buffer Devices <Nov94...
**82C822 PCIB (VLB-to-PCI bridge) c:94...
**Other:...
*PC CHIPS/Amptron/Atrend/ECS/Elpina/etc...
*SIS...
*Symphony...
*TI (Texas Instruments)...
*UMC...
*Unresearched:...
*VIA...
*VLSI...
*Western Digital...
*Winbond...
*ZyMOS...
*General Sources:...
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