[Home] [This version is outdated, a new version is here]
*Title...
*Search:...
*Read Me/FAQ/General Info...
*_IBM...
*ACC Micro...
*ALD...
*ALi...
*AMD . . . . . . . [no datasheets, some info]...
*Chips & Technologies...
*Contaq . . . . . [no datasheets, some info]...
*Efar Microsystems [no datasheets, some info]...
*ETEQ...
*Faraday...
*Forex . . . . . . [List only, no datasheets found]...
*Intel...
**IBM PC/XT/AT Chip Sets
***Datasheets:...
***Read Me:...
***Overview (History):...
***Summary of sections:...
***§1: Intel MCS-8x/iAPX Microprocessor families:...
***§2: Intel Chip Specifications 1975 - Jan 1982:...
***§3: IBM PC/XT: Original system chips: ...
***§4: Intel Chip Specifications Jan 1982 - Jan? 1984...
***§5: IBM AT: Original system chips:...
***§6: Intel Chip Specifications Jan? 1984 - 1989...
**82230/82231 High Integration AT-Compatible Chip Set(ZyMOS) c:Aug88...
**82310 Micro Channel Compatible Peripheral Chip Set 04/21/88...
**82311 High Integration MCA Compatible Perip. Chip Set 11/14/88...
**82320 MCA compatible Chipset [no datasheet] 04/10/89...
**82340DX Chip Set (VLSI) (82346/82345/82355) 01/08/90...
**82340SX Chip Set (VLSI) (82343/82344) 01/25/89...
**82350 EISA Chip Set 07/10/89...
**82350DT EISA Chip Set 04/22/91...
**82420TX/ZX PCIset (for 486) TX (Saturn), ZX (Saturn II) c:Nov92...
**82420EX PCIset (for 486) EX (Aries) (82425EX/82426EX) <Dec94...
**82430LX PCIset (Pentium) LX (Mercury) (82433LX/82434LX) 03/22/93...
**82430NX PCIset (Pentium) NX (Neptune) (82433NX/82434NX) Mar94...
**82430FX PCIset (Pentium) FX (Triton I) (82437FX/82438FX)01/31/95...
**82430MX PCIset (Pentium) MX (Mobile Triton)(82437/438MX)11/01/95...
**82430HX PCIset (Pentium) HX (Triton II) (82439HX) 02/12/96...
**82430VX PCIset (Pentium) VX (Triton II) (82437VX/82438) 02/12/96...
**82430TX PCIset (Pentium) TX (Triton II) (82439TX) 02/17/97...
**82450KX/GX PCIset (Pentium Pro) KX/GX (Mars/Orion) 11/01/95...
**
**Support Chips:
**82091AA Advanced Interface Peripheral (AIP) c93...
**8289 Bus Arbiter (808x) c79...
**82289 Bus Arbiter for iAPX 286 Processor Family c83...
**82258 Advanced Direct Memory Access Coprocessor(ADMA) 01/01/84...
**82335 High-Integration Interface Device For 386SX c:Nov88...
**82360SL I/O Subsystem 10/05/90...
**82370 Integrated System Peripheral (for 82376) c:Oct88...
**82371FB/SB PCI ISA IDE Xcelerator 82371FB/82371SB (PIIX/3) 01/31/95...
**82371MX Mobile PCI I/O IDE Xcelerator (MPIIX) 11/01/95...
**82371AB PCI-TO-ISA / IDE Xcelerator 82371AB (PIIX4) 02/17/97...
**82374/82375 PCI-EISA Bridge (82374EB/82375EB, 374SB/375SB) c:Mar93...
**82378 System I/O (SIO) (82378IB and 82378ZB) c:Mar93...
**82379AB System I/O-APIC (SIO.A) <Dec94...
**82380 32-bit DMA Controller w/ Integrated Peripherals 02/01/87...
**82380FB/AB PCIset: 82380FB Mobile PCI-to-PCI Bridge(MPCI2) 02/17/97...
**82384 Clock Generator and Reset Interface c86...
**82385 32-bit Cache Controller for 80386 09/29/87...
**82385SX 32-bit Cache Controller for 80386SX 01/25/89...
**82395DX High Performance Smart Cache 06/18/90...
**82395SX Smart Cache 12/17/90...
**82396SX Smart Cache 12/17/90...
**82485 Turbo Cache (and 485Turbocache) c90...
**82489DX Advanced Programmable Interrupt Controller 10/12/92...
**82495DX/490DX DX CPU-Cache Chip Set <Sep91
***Notes:...
***Info:...
***Configurations:...
***Features:...
**82495XP/490XP Cache Controller / Cache RAM (for i860) 06/05/91...
**82496/491 Cache Controller / Cache RAM (for P5 Pentium) 03/22/93...
**82497/492 Cache Controller / Cache RAM (for P54 Pentium) <Nov94...
**82498/493 Cache Controller / Cache RAM (for P54 Pentium) <Nov94...
**
**Later chipsets (basic spec):
**440 series:...
**450NX (?) 06/29/98:...
**????? (Profusion) c:99...
**800 series...
*Headland/G2...
*HMC (Hulon Microelectronics)...
*Logicstar...
*Motorola...
*OPTi...
**82C281/282 Cache Sx/AT (386SX) <08/22/91
***Notes:...
***Info:
The 82C281/2 is a highly integrated AT system logic VLSI for high end
386 Sx AT systems. It integrates the logic for local DRAM control, AT
bus control, cache memory control, and data bus control and is
designed for systems running at 16MHz, 20MHz, and 25MHz.
A high performance, compact 386 Sx/AT system can be implemented easily
with 82C281/2 and standard peripheral controllers like the 82C206 or
the VLSI 82C100 plus Dallas Semiconductor DS1287.
2 System Operation
The following sections describe the detailed system operations of the
82C281 /2 based Sx-AT design.
2.1 Reset
The power good (PWRGD) signal from power supply drives the system into
the initial state when it is asserted low. The 82C281/2 forces CPURST,
SYSRST, and NPRST high as soon as PWRGD becomes inactive. When the
PWRGD is high, the chip deactivates the CPURST, SYSRST, and NPRST
after 128 CLK2 cycles.
2.2 Cache Interface
The 82028112 cache control unit monitors the HIT# pin and the internal
NCA# signals to determine if it is a cache hit or cache miss
cycle. During the cache read miss cycle, the cache controller asserts
TAGWE# to update the TAG RAM, CAWE# is also asserted to update the
cache data memory.
The A1 CNT output will be forced high then low to toggle CPU address
bit 1 to cache data memory to achieve the prefetch.
During cache write hit cycles, the cache controller asserts the CAWE#
signal to update the cache data memory.
2.3 Local DRAM Interfaces
Local DRAM is located on the CPU local data bus and is buffered by a
F244 and F373 buffer. During CPU read cycles data is routed from main
memory to CPU through F244’s Which are controled by LMRD#. During CPU
write cycles, data is latched by F373 latches with the PDLTH signal
from the 82C281/2 while DWE# controls the transceivers' enable. The
main memory subsystem asserts the LMRD# while CPU, DMA, and external
master card reads the local DRAM. DWE# is asserted during local DRAM
memory write.
For local memory read cycles, the memory controller reads two bytes at
a time. The read data passes into 82C281/2 where the parity checking
function is executed.
For the local memory write cycles, the data bus control unit generates
the parity bits to be stored into the local DRAM.
2.4 System BIOS ROM
If the system BIOS ROM is not shadowed, the ROM cycles are treated as
AT cycles. The system designer can put the ROM on the XD bus as an
8-bit slave or SD bus as a 16-Bit slave.
For a 16-bit slave, ROMCS# is connected to M16# through an open
collector driver such as a 7407, the 82C281/2 monitors M16# to
determine the width of the ROM data path.
2.5 I/O Ports located on the XD bus
For l/O ports located on the XD bus, the XDIR# is activated. I/O ports
0F0H - 0FFH are reserved for the coprocessor.
2.6 Refresh Cycles
The AT bus control unit arbitrates the hold request from 82C206 and
the refresh request from 82C281/2 internal, then decides which is the
next owner of the bus once the CPU relinquishes it. The refresh
request generated internally by 82C281/2 can be programmed as every
15.9 micro-seconds or every 95.5 micro-seconds for slow refresh
DRAM. lf the bus is granted for refresh cycles, the AT bus control
unit asserts RFSH# and MEMRD# commands and also generates the refresh
address.
2.7 DMA Cycles
The hold request from the 82C206 initiates DMA/Master transfers. The
82C281/2 performs the arbitration between HRQ and refresh
request. After the CPU acknowledges by asserting HLDA, and DMA request
wins the arbitration, the 82C281/2 sends HLDA1 to the 82C206
acknowledging the request. The 820206 then asserts DMA16# and
activates ADS16# to start 16-bit DMA transfers, or asserts DMA8# and
activates ADS8# to start 8-bit DMA transfers.
***Configurations:...
***Features:...
**82C283 386SX System Controller c:91...
**82C291 SXWB PC/AT Chipset (386SX) c:91...
**82C295 SLCWB PC/AT Chipset (386SX) ?...
**82C381/382 HiD/386 (386DX) c:89...
**82C391/392 386WB PC/AT Chipset (386DX) <Dec90...
**82C461/462 Notebook PC/AT chipset [no datasheet] ?...
**82c463 SCNB Single Ship Notebook c:92...
**82c465MV/A/B Single-Chip Mixed Voltage Notebook Solution <Oct97...
**82C481?/482? HiP/486 & HiB/486 [no datasheet] Oct89...
**82C491/392 486WB PC/AT Chipset <04/21/91...
**82C493/392 486SXWB <10/21/91...
**82C495SX/392SX LCWB PC/AT chipset [no datasheet] ?...
**82C495SLC DXSLC 386/486 Low Cost Write Back c:92...
**82C495XLC PC/AT Chip Set c:93...
**82c496A/B DXBB PC/AT Chipset <Mar92...
**82C496/7 DXBB PC/AT Chipset (Cached) <01/16/92...
**82C498 DXWB PC/AT chipset [no datasheet] ?...
**82C499 DXSC DX System Controller c:93...
**82C546/547 Python PTM3V c:94...
**82C556/7/8 Viper [no datasheet] ?...
**82C556/7/8N Viper-N Viper Notebook Chipset <05/25/95...
**82C556M/7M/8E Viper-N+ Viper Notebook Chipset c:96...
**82C566/7/8 Viper-Max Chipset Scalable MultiMedia PC Solution ?...
**82C571/572 486/Pentium c:93...
**82C576/7/8 Viper Xpress [no datasheet] ?...
**82C576/8/9 Viper XPress+ [no datasheet, some info] <01/16/97...
**82C596/597 PTMAWB Pentium Adaptive Write-back (Cobra) c:93...
**82C650/1/2 Discovery (Pentium Pro) [no datasheet] ?...
**82C681/2/6/7 386/486WB EISA c:92...
**82C683 386/486AWB EISA [no datasheet] ?...
**82C693/6/7 Pentium uP Write Back Cache EISA c:93...
**82C700 FireStar c:97...
**82C701 FireStar Plus c:97
***Notes:...
***Info:...
***Configurations:...
***Features:...
**82C750 Vendetta [no datasheet] ?...
**82c801 SCWB2 DX Single Chip Solution c:92...
**82C802 SCWB2 PC/AT Single Chip [no datasheet] ?...
**82C802G/GP System/Power Management Controller (cached) c:93...
**82C895 System/Power Management Controller (cached) c:Sep94...
**82C898 System/Power Management Controller (non-cache)c:Nov94...
**
**Support Chips:
**82C601/2 Buffer Devices <Nov94...
**82C822 PCIB (VLB-to-PCI bridge) c:94...
**Other:...
*PC CHIPS/Amptron/Atrend/ECS/Elpina/etc...
*SIS...
*Symphony...
*TI (Texas Instruments)...
*UMC...
*Unresearched:...
*VIA...
*VLSI...
*Western Digital...
*Winbond...
*ZyMOS...
*General Sources:...
(c) Copyright mR_Slugs Warehouse - All rights Reserved