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**DISCLAIMER!

  THE DOCUMENT IS PROVIDED "AS IS", WITH ABSOLUTELY NO WARRANTY OF ANY
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  WARRANTIES OF MERCHANTABILITY, FITNESS  FOR A PARTICULAR PURPOSE AND
  NONINFRINGEMENT. IN NO EVENT SHALL  THE AUTHORS OR COPYRIGHT HOLDERS
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  ACTION OF  CONTRACT, TORT OR OTHERWISE,  ARISING FROM, OUT OF  OR IN
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  DOCUMENT.

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**82489DX       Advanced Programmable Interrupt Controller    10/12/92
***Notes:...
***Info:...
***Versions:...
***Features:...
**82495DX/490DX DX CPU-Cache Chip Set                           <Sep91...
**82495XP/490XP Cache Controller / Cache RAM (for i860)       06/05/91...
**82496/491     Cache Controller / Cache RAM (for P5 Pentium) 03/22/93...
**82497/492   Cache Controller / Cache RAM (for P54 Pentium)    <Nov94...
**82498/493   Cache Controller / Cache RAM (for P54 Pentium)    <Nov94...
**
**Later chipsets (basic spec):
**440 series:...
**450NX  (?)            06/29/98:...
**?????  (Profusion)    c:99...
**800 series...
*Headland/G2...
*HMC (Hulon Microelectronics)...
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*OPTi...
**82C556M/7M/8E  Viper-N+ Viper Notebook Chipset                  c:96
***Notes:...
***Info:...
***Configurations:...
***Features:...
**82C566/7/8     Viper-Max Chipset Scalable MultiMedia PC Solution   ?...
**82C571/572     486/Pentium                                      c:93...
**82C576/7/8     Viper Xpress  [no datasheet]                        ?...
**82C576/8/9     Viper XPress+ [no datasheet, some info]     <01/16/97...
**82C596/597     PTMAWB Pentium Adaptive Write-back (Cobra)       c:93
***Notes::...
***Info:...
***Configurations:...
***Features:
o   100% PC/AT compatible 
o   Fully supports the Intel Pentium microprocessor 
o   Three chip PC/AT solution: 82C596, 82C597 and 82C206 
o   Supports Intel Pentium CPU address pipelining 
o   IX clock source, supporting systems running up to 66 MHz 
o   Adaptive Write Back, direct-mapped cache with size 
    selections: 64K, 128K, 256K, 512K, 1Mb, 2Mb 
o   Programmable cache write policy: adaptive write back (AWB), 
    write-back or write through 
o   Fully programmable cache and DRAM read/write cycles 
o   Supports 3-2-2-2 cache burst read cycle at 66 MHz 
o   Built-in TAG auto-invalidation circuitry 
o   Support for two programmable non-cacheable/system memory "hole" 
    regions 
o   Supports two banks of 64-bit wide DRAMs with 256K, 
    512K, 1 M, 2M, 4M, and 8M x 36 page-mode DRAMs 
o   Supports DRAM configurations up to 128 Mb 
o   Supports 3-3-3-3 pipeline DRAM burst cycles 
o   DRAM post write buffer 
o   Provides Flash ROM support 
o   33 MHz asynchronous 32-bit VESA VL Local Bus support 
o   Performance oriented snoop-line comparator for VL/ISA bus masters 
o   Extended DMA page register 
o   Asynchronous CPU and VL bus interface 
o   AT bus clock speed programmability 
o   Low power, high speed CMOS technology 

**82C650/1/2     Discovery (Pentium Pro) [no datasheet]              ?...
**82C681/2/6/7   386/486WB EISA                                   c:92...
**82C683         386/486AWB EISA [no datasheet]                      ?...
**82C693/6/7     Pentium uP Write Back Cache EISA                 c:93...
**82C700         FireStar                                         c:97...
**82C701         FireStar Plus                                    c:97...
**82C750         Vendetta      [no datasheet]                        ?...
**82c801         SCWB2 DX Single Chip Solution                    c:92...
**82C802         SCWB2 PC/AT Single Chip [no datasheet]              ?...
**82C802G/GP     System/Power Management Controller (cached)      c:93...
**82C895         System/Power Management Controller (cached)   c:Sep94...
**82C898         System/Power Management Controller (non-cache)c:Nov94...
**
**Support Chips:
**82C601/2       Buffer Devices                                 <Nov94...
**82C822         PCIB (VLB-to-PCI bridge)                         c:94...
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