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**82495XP/490XP Cache Controller / Cache RAM (for i860) 06/05/91
***Notes:...
***Info:...
***Features:...
**82496/491 Cache Controller / Cache RAM (for P5 Pentium) 03/22/93...
**82497/492 Cache Controller / Cache RAM (for P54 Pentium) <Nov94...
**82498/493 Cache Controller / Cache RAM (for P54 Pentium) <Nov94...
**
**Later chipsets (basic spec):
**440 series:...
**450NX (?) 06/29/98:...
**????? (Profusion) c:99...
**800 series
***810 (Whitney) 04/26/99...
***810L (Whitney) 04/26/99...
***810-DC100 (Whitney) 04/26/99...
***810e (Whitney) 09/27/99...
***810e2 (Whitney) 01/03/01...
***815 (Solano) 06/19/00...
***815e (Solano-2) 06/19/00...
***815em (Solano-?) 10/23/00...
***815ep (Solano-3) c:Nov'00...
***815p (Solano-3) c:Mar'01...
***815g (Solano-3) c:Sep'01...
***815eg (Solano-3) c:Sep'01...
***820 (Camino) 11/15/99...
***820e (Camino-2) 06/05/00...
***830M (Almador) 07/30/01...
***830MP (Almador) 07/30/01...
***830MG (Almador) 07/30/01...
***840 (Carmel) 10/25/99...
***845 (Brookdale) 09/10/01...
***845MP (Brookdale-M) 03/04/02...
***845MZ (Brookdale-M) 03/04/02...
***845E (Brookdale-E) 05/20/02...
***845G (Brookdale-G) 05/20/02...
***845GL (Brookdale-GL) 05/20/02...
***845GE (Brookdale-GE) 10/07/02...
***845PE (Brookdale-PE) 10/07/02...
***845GV (Brookdale-GV) 10/07/02...
***848P (Breeds Hill) c:Aug'03...
***850 (Tehama) 11/20/00...
***850E (Tehama-E) 05/06/02...
***852GM (Montara-GM) 01/14/03...
***852GMV (Montara-GM) ???...
***852PM (Montara-GM) 06/11/03...
***852GME (Montara-GM) 06/11/03...
***854 (?) 04/11/05...
***855GM (Montara-GM) 03/12/03...
***855GME (Montara-GM) 03/12/03...
***855PM (Odem) 03/12/03...
***860 (Colusa) 05/21/01...
***865G (Springdale) 05/21/03...
***865PE (Springdale-PE) 05/21/03...
***865P (Springdale-P) 05/21/03...
***865GV (Springdale-GV) c:Sep'03...
***875P (Canterwood) 04/14/03...
*Headland/G2...
*HMC (Hulon Microelectronics)...
*Logicstar...
*Motorola...
*OPTi...
**82c465MV/A/B Single-Chip Mixed Voltage Notebook Solution <Oct97
***Info:...
***Configurations:...
***Features:
****MV
CPU and VL-Bus Features
o Supports AMD, Cyrix, Intel, and IBM 486-type 32-bit CPUs, in
3.3V or 5.0V, including clock-tripled technology.
o Provides a fail-safe thermal management scheme that predicts when
CPU temperature is rising to unsafe levels and forces the system
into a slower operating mode (cool-down clocking).
o Provides fast emulation of keyboard controller CPU reset and gate
A20 control; supports Port 092h as well.
o Fully supports local bus implementations, including VL-bus
masters.
o Offers complete Microsoft APM (Advance Power Management)
operability, with CPU stop clock support available.
o Supports next generation processor stop clock protocol, to take
advantage of the performance improvement possible when PLL
start-up delay is reduced from milliseconds to nanoseconds.
o Engages automatic internal resistors to eliminate the need for
external pull-up/pull-down resistors on CPU address, data, and
control lines.
o Provides SMBASE relocation to match the feature found in some
CPUs that allows the SMBASE to be reprogrammed; each 64KB segment
can be remapped to any 64KB-boundary segment in the first 640KB
of address space.
o Offers PCI compatibility in that the 82C465MV is fully compatible
with the OPTi 82C832 PCI peripheral bridge, providing bus master
support as well.
o With the core operating at 5.0V , runs as fast as 50MHz with:
- CPU and ISA bus I/O at 5.0V
- CPU at 3.3V and ISA bus I/O at 5.0V
o With the core operating at 3.3V, runs as fast as 40MHz with:
- CPU and ISA bus I/O at 3.3V
DRAM/Cache Controller Features
The DRAM controller of the 82C465MV Single-Chip Notebook chipset runs
from a 1X clock. It provides all of the performance features popular
on powerful desktop systems and integrates power control for efficient
operation.
o Provides L1 cache support for an on-CPU writeback cache such as
that found on the Cyrix Cx486DX/DX2 processor and L1 writeback
CPUs from Intel and AMD.
o Provides power-managed L2 cache support with a high-performance,
writeback external cache using the proven OPTi desktop 32-bit
cache controller. Integral power control turns on the chip select
lines only to cache chips actually being accessed, resulting in
extremely low active-mode power consumption. Moreover, the cache
can be flushed and completely turned off during low-power Suspend
mode.
o Operates up to five banks of DRAM, supporting any memory type in
any bank, along with bank skipping (of intermediate banks) for
automatic BIOS-based disabling of defective DRAM.
o Uses simplified memory programming scheme that sup-ports up to
12x12 symmetrical along with asymmetrical DRAM such as 11x9 and
12x8 configurations. Symmetrical and asymmetrical types can
be mixed.
o Allows any bank to use 256Kb , 512Kb , 1Mb , 2Mb , 4Mb , 8Mb ,
or 16Mb DRAM devices.
o Page mode DRAM controller supports 3-2-2-2 , 4-3-3-3 , and
5-4-4-4 burst read memory cycles , zero or one wait state DRAM
write cycles.
o Supports two programmable non-cacheable regions
o Offers fully programmable shadowing of ROM using DRAM in the
C0000-FFFFFh region.
o Allows write-protected shadowing and caching of system and
video BIOS.
o Allows normal or slow refresh, CAS-before-RAS refresh, and self-
refresh DRAM support; minimum-pulse refresh cycles save power
during Suspend mode.
ISA Bus Features
The ISA bus interface of the 82C465MV chip offers many improvements
over previous generation OPTi notebook chipsets and competitive
notebook chipsets
o The internal 82C206 IPC offers a true single-chip note-book
implementation and is based on the proven 82C463MV core.
o The 82C465MV implements a complete ISA-compatible system with only
one extra device, the OPTi 82C602 Note-book Companion chip, which
contains a Real Time Clock (RTC) with 256 bytes of non-volatile
(backed up by battery) RAM and the equivalent of seven discrete
TTL devices.
o The logic integrates an enhanced IDE interface running at local-
bus speeds (100% speed increase typical) based on the proven OPTi
82C611 core.
o Integral IDE support uses one external 74244 TTL device to
control the IDE, with a second 7416245 device optional for
complete power-down isolation of the IDE drive while the
system is active. Dual drive support is also available.
o The IDE command scheme shares no ISA bus command lines , to
prevent incompatibility with other ISA bus devices due to illegal
"short pulse" cycles on ISA bus.
o 8.00MHz ISA bus operation is available for implementations
requiring exact adherence to the original ISA standard.
o 16-bit decoding for internal I/O prevents conflicts for I/O
peripherals addressed above 100h.
o Four programmable chip selects each decode ten address lines,
A[9:0] for I/O addressing or A[23:14] for memory addressing.
Memory address decoding allows simplified ROM chip select
generation for applications such as Windows CE.
Power Management Features
The synergistic incorporation of power management and system control
features with the standard ISA subsystem con-troller of the 82C465MV
chipset results in a compact design that handles multiple tasks with a
simple, common interface.
The power management interrupt (PMI) scheme provides system management
code with a quick means of identifying and handling events that affect
power control and consumption.
o Recognizes 28 separate PMI events. Within these events, many sub-
events are also identifiable for a high degree of power management
monitoring flexibility.
o Eleven of the PMI events have individual timers to indicate inact-
ivity time-out situations.
o Eight external inputs are available for monitoring asynchronous
system events. These are in addition to the ISA-compatible IRQ
lines that can also be monitored as power management events.
o PMI generation on access allows SMI code to intercept status
queries to powered-down devices that do not actually need to be
restarted simply to return an "Idle" status.
o Activity tracking register of eight events allows SMI or non-SMI
applications a means of determining whether activity has occurred
since the last time the register was checked. Polling for I/O
activity can then be used instead of multiple SMIs for less
significant events.
o Memory watchdog monitoring allows accesses to memory ranges
(specified as programmed) to cause an SMI. ISA bus memory devices
that are not being accessed can be programmed to cause a time-out
SMI so that unused peripherals can be powered down.
o Supports system-level low-power Suspend, low-power Suspend with
zero-volt CPU Suspend, or total system zero-volt Suspend.
o Twelve peripheral power control pins plus four user-definable I/O
pins provides exceptional flexibility in peripheral device
control.
o RTC alarm or modem ring can wake up the system from low-power
Suspend mode.
o Suspend current leakage control ensures that negligible power will
be consumed in Suspend mode without additional external buffering.
Backward Compatibility Features
The 82C465MV is application-compatible with the 82C463MV for the vast
majority of applications.
o The register set and logic are derived from and are a superset of
the popular OPTi 82C463MV notebook chipset.
o When used as a drop-in replacement for the 82C463MV, the 82C465MV
allows continued operation with no required changes to the
original 82C463MV BIOS. Optional programming needed to take
advantage of performance improvements of 82C465MV logic can be run
from an executable file.
o Many of the new 82C465MV features can be utilized with only minor
changes to the 82C463MV BIOS; more extensive use of the new
feature set requires some changes to hardware design as well.
o BIOS code need only check a single register to learn whether it is
running on the 82C465MV or on an 82C463/463MV chipset.
****MVA...
****MVB:...
**82C481?/482? HiP/486 & HiB/486 [no datasheet] Oct89...
**82C491/392 486WB PC/AT Chipset <04/21/91...
**82C493/392 486SXWB <10/21/91...
**82C495SX/392SX LCWB PC/AT chipset [no datasheet] ?...
**82C495SLC DXSLC 386/486 Low Cost Write Back c:92...
**82C495XLC PC/AT Chip Set c:93...
**82c496A/B DXBB PC/AT Chipset <Mar92...
**82C496/7 DXBB PC/AT Chipset (Cached) <01/16/92...
**82C498 DXWB PC/AT chipset [no datasheet] ?...
**82C499 DXSC DX System Controller c:93...
**82C546/547 Python PTM3V c:94...
**82C556/7/8 Viper [no datasheet] ?...
**82C556/7/8N Viper-N Viper Notebook Chipset <05/25/95...
**82C556M/7M/8E Viper-N+ Viper Notebook Chipset c:96...
**82C566/7/8 Viper-Max Chipset Scalable MultiMedia PC Solution ?...
**82C571/572 486/Pentium c:93...
**82C576/7/8 Viper Xpress [no datasheet] ?...
**82C576/8/9 Viper XPress+ [no datasheet, some info] <01/16/97...
**82C596/597 PTMAWB Pentium Adaptive Write-back (Cobra) c:93...
**82C650/1/2 Discovery (Pentium Pro) [no datasheet] ?...
**82C681/2/6/7 386/486WB EISA c:92...
**82C683 386/486AWB EISA [no datasheet] ?...
**82C693/6/7 Pentium uP Write Back Cache EISA c:93...
**82C700 FireStar c:97...
**82C701 FireStar Plus c:97...
**82C750 Vendetta [no datasheet] ?...
**82c801 SCWB2 DX Single Chip Solution c:92...
**82C802 SCWB2 PC/AT Single Chip [no datasheet] ?...
**82C802G/GP System/Power Management Controller (cached) c:93...
**82C895 System/Power Management Controller (cached) c:Sep94...
**82C898 System/Power Management Controller (non-cache)c:Nov94...
**
**Support Chips:
**82C601/2 Buffer Devices <Nov94...
**82C822 PCIB (VLB-to-PCI bridge) c:94...
**Other:...
*PC CHIPS/Amptron/Atrend/ECS/Elpina/etc...
*SIS...
*Symphony...
*TI (Texas Instruments)...
*UMC...
*Unresearched:...
*VIA...
*VLSI...
*Western Digital...
*Winbond...
*ZyMOS...
*General Sources:...
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