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**'chip set', 'chip-set' or 'chipset'?
I don't know, all seem to be ok/OK/okay. CHIPset is a term used by
C&T.
**What's not included:...
**Who made the first chip set?...
**Spelling errors/mistyped words
Yes, I know there are spelling errors, and things are mistyped. It
seems no matter how hard I try my fingers hit 't' twice when typing
'compatible' rendering it 'compattible' numerous, (thousands actually)
times. I don't have the time or the will to check the spelling of
everything. Basic spell checking has been peformed. Please let me know
if there is anything that would lead to incorrect information, or
something is so mangled that it needs revising. But if you can
basically understand what was intended, just cope with it. Just
cope:-)
BTW, "110" port is an "I/O" port that has been OCRed badly, as is an
"1/0" port.
**Info needed on:...
**A note on VESA support of 486 chipsets....
**Datasheets:...
*_IBM...
*ACC Micro...
*ALD...
*ALi...
*AMD . . . . . . . [no datasheets, some info]...
*Chips & Technologies...
*Contaq . . . . . [no datasheets, some info]...
*Efar Microsystems [no datasheets, some info]...
*ETEQ...
*Faraday...
*Forex . . . . . . [List only, no datasheets found]...
*Intel...
**82495DX/490DX DX CPU-Cache Chip Set <Sep91
***Notes:...
***Info:...
***Configurations:...
***Features:...
**82495XP/490XP Cache Controller / Cache RAM (for i860) 06/05/91...
**82496/491 Cache Controller / Cache RAM (for P5 Pentium) 03/22/93...
**82497/492 Cache Controller / Cache RAM (for P54 Pentium) <Nov94...
**82498/493 Cache Controller / Cache RAM (for P54 Pentium) <Nov94...
**
**Later chipsets (basic spec):
**440 series:...
**450NX (?) 06/29/98:...
**????? (Profusion) c:99...
**800 series...
*Headland/G2...
*HMC (Hulon Microelectronics)...
*Logicstar...
*Motorola...
*OPTi...
**82C822 PCIB (VLB-to-PCI bridge) c:94
***Notes:...
***Info:...
***Versions:...
***Features:
o Fully compliant to the PCI V2.0 Specification
o Up to four PCI masters
o Supports system operational speeds of 25, 33, 40, and 50MHz
o Provides central arbiter to arbitrate the bus requests between:
- host CPU
- PCI masters
- DMA/ISA masters
- Refresh
o Offers programmable priority scheme for both the central arbiter
and DMA channels:
- Fixed
- Rotating
- Fixed/Rotating combination
o Burst mode PCI accesses to local memory support
o Combine host CPU sequential writes into PCI burst write cycles
o Interfaces with all OPTi's VL chipset solutions
o Single 208-pin PQFP (Plastic Quad Flat Pack)
**Other:...
*PC CHIPS/Amptron/Atrend/ECS/Elpina/etc...
*SIS...
*Symphony...
*TI (Texas Instruments)...
*UMC...
*Unresearched:...
*VIA...
*VLSI...
*Western Digital...
*Winbond...
*ZyMOS...
*General Sources:...
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