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**82C596/A 3/486 Writeback Cache [no datasheet] <11/11/92
Possibly two variant, or one version with two names, one being a
shorthand:
82C596
82C596A
ftp://ami.com/archive/Other_Manuals/!index.txt
lists the A variant with the date 11/11/92. No date for non-A:
"
CTQ596.Z06 88900 12-21-92 3/486 Contaq 596 chipset 06-06 core
CTQ596A.Z11 95383 10-07-93 3/486 Contaq 596-A for 11/11/92
CTQ596_3.Z06 92195 03-01-93 386 Contaq 596
CTQ596_3.Z11 98031 06-21-93 386 Contaq 596
CTQ596_4.Z06 92236 03-01-93 486 Contaq 596
CTQ596_4.Z11 97602 06-21-93 486 Contaq 596
CT596A.Z08 96217 12-09-93 Contaq 596a
"
Note, the column of dates is the file date.
**?????? 486 EISA chipset [no datasheet] <Feb93...
**82C599 PCI-VLB Bridge [no datasheet, some info] ?...
**82C693 PCI-ISA Bridge [no datasheet] ?...
*Efar Microsystems [no datasheets, some info]...
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*Forex . . . . . . [List only, no datasheets found]...
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**82489DX Advanced Programmable Interrupt Controller 10/12/92
***Notes:...
***Info:...
***Versions:...
***Features:...
**82495DX/490DX DX CPU-Cache Chip Set <Sep91...
**82495XP/490XP Cache Controller / Cache RAM (for i860) 06/05/91...
**82496/491 Cache Controller / Cache RAM (for P5 Pentium) 03/22/93...
**82497/492 Cache Controller / Cache RAM (for P54 Pentium) <Nov94...
**82498/493 Cache Controller / Cache RAM (for P54 Pentium) <Nov94...
**
**Later chipsets (basic spec):
**440 series:...
**450NX (?) 06/29/98:...
**????? (Profusion) c:99...
**800 series...
*Headland/G2...
**HT12/+/A Single 286 AT Chip with EMS support c:Aug90
***Info:
The HT12, an IBM PC/AT compatible chip, supports the 80286 CPU at
clock speeds to 16MHz. This highly integrated chip solution offers
high performance and reliability, with low cost, minimal power
consumption, and low board-space requirements. It differs from the
HT11 by the addition of 4 EMS Registers and an EMS Software Driver.
A fully PC/AT compatible system is implemented with this chip by
adding a CPU/NPU, KBD CNTRL, RTC, BIOS, Memory and a few low cost TTL
devices.
This chip supports 64K, 256K and 1M, x1 and x4, DRAMs in config-
urations up to 4 Meg. A 12.5MHz 0 wait-state system can be imple-
mented using 80ns DRAMs while a 10MHz 0 wait-state system requires
100ns DRAMs. The memory controller also supports the shadow RAM
feature and the Split Memory option. The Split Memory option allows
the System RAM located between 640K and 1M to be remapped above top of
memory.
The HT12 contains CPU and peripheral support functions; including DMA
controllers, a memory mapper, timer/counters, interrupt controllers,
and a bus controller. This chip replaces board address buffers, data
transceivers, memory drivers, parity generators and their support
circuits. This chip is packaged in a 160 pin Flat Pack.
***Configurations:...
***Features:...
**HT18 80386SX Single Chip c:Sep91...
**HT21 386SX/286 Single Chip (20 MHz) c:Aug91...
**HT22 386SX/286 Single Chip (25 MHz) c:Sep91...
**HT25 3-volt Core Logic for 386SX c:Dec92...
**HT35 Single-Chip Peripheral Controller [partial info] ?...
**HTK320 386DX Chip Set c:Sep91...
**HTK340 "Shasta" 486 Chip Set c:Jun92...
**Support Chips:
**HT44 Secondary Cache c:Jun92
***Info:...
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