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*_IBM...
*ACC Micro...
**ACC2046/ST 486DX/486SX/386DX Single Chip AT                   <Jul92
***Info:...
***Configurations:...
***Features:...
**ACC2048    WB 486 Notebook/Embedded Single Chip [no datasheet]     ?...
**ACC2051/NT PCI Single Chip Solution for Notebook Applications    c96...
**ACC2056    ?Pentium 3.3V Notebook               [no datasheet]<Jan96...
**ACC2057    PCI Notebook/Embedded Single Chip    [no datasheet]<Aug96...
**ACC2066NT  486 Notebook/Embedded Single Chip    [no datasheet]     ?...
**ACC2086    486 VL-based System Super Chip Soluti[no datasheet]     ?...
**ACC2087    Enhanced Super Chip (486 Single Chip)              <Aug96...
**ACC2089    486 PCI-based System Super Chip      [no datasheet]     ?...
**ACC2168/GT 32-bit 486 Green System Single Chip  [no datasheet]     ?...
**ACC2178A   32-bit 486 Green System Single Chip  [no datasheet]     ?...
**ACC2268    ?486                                 [no datasheet]     ?...
**ACC????    Maple/Maple-133 486-System-On-Chip   [no datasheet]     ?...
**
**Support Chips:
**ACC2016    Buffer and MUX Logic                                  c96...
**ACC2020    Power Management Chip                                 c92...
**ACC5500    Multifunction I/O Control Chip for PS2 Model 50/60    c88...
**
**Other chips...
*ALD...
*ALi...
*AMD . . . . . . . [no datasheets, some info]...
*Chips & Technologies...
*Contaq  . . . . . [no datasheets, some info]...
*Efar Microsystems [no datasheets, some info]...
*ETEQ...
*Faraday...
*Forex . . . . . . [List only, no datasheets found]...
*Intel...
**82495DX/490DX DX CPU-Cache Chip Set                           <Sep91
***Notes:...
***Info:...
***Configurations:...
***Features:
o   50 MHz Intel486 DX CPU 
    - RISC Integer Core with Frequent Instructions Executing in One 
      Clock
    - 160 Mbyte/Sec Burst Bus
    - 41 Dhrystone MIPs
    - 11.5M Double Precision Whetstones/Sec.
    - On-Chip Cache and FPU
o   Highly Flexible
    - Supports 128 Kbyte and 256 Kbyte Configurations
    - Complete MESI Protocol Support
    - 32- or 64-Bit Memory Bus Width
    - Synchronous, Asynchronous, and Strobed Memory Bus Protocols
    - Variable Cache Line Sizes and Sectoring
    - Cache Data Parity Option
o   High Performance Second Level Cache
    - Two-Way Set Associative
    - Write-Back or Write Through Cache
    - Zero Wait State Cache Access
    - Concurrent CPU Bus, Memory Bus, and Internal Array Operation
o   Full Multiprocessing Support
    - Implements MESI Write-Back Cache Protocol
    - Low Bus Utilization
    - Automatically Maintains 1st Level Cache Consistency
    - Supports Read-for-Ownership, Write-Allocation, and Cache-to-
      Cache Transfers

**82495XP/490XP Cache Controller / Cache RAM (for i860)       06/05/91...
**82496/491     Cache Controller / Cache RAM (for P5 Pentium) 03/22/93...
**82497/492   Cache Controller / Cache RAM (for P54 Pentium)    <Nov94...
**82498/493   Cache Controller / Cache RAM (for P54 Pentium)    <Nov94...
**
**Later chipsets (basic spec):
**440 series:...
**450NX  (?)            06/29/98:...
**?????  (Profusion)    c:99
Chips:         
Memory Access Controller (MAC)  
Data Interface Buffer (DIB)
CPUs:          8x P-III Xeon Oct
DRAM Types:    SDRAM PC100 2-way Interleave dual channel
Max Mem:       32GB
ECC/Parity:    ECC
AGP speed:     N/A
Bus Speed:     100
PCI Clock/Bus: 1/3 PCI-66/64



**800 series...
*Headland/G2...
**HT25          3-volt Core Logic for 386SX                    c:Dec92
***Info:...
***Configurations:...
***Features:...
**HT35          Single-Chip Peripheral Controller [partial info]     ?...
**HTK320        386DX Chip Set                                 c:Sep91...
**HTK340        "Shasta" 486 Chip Set                          c:Jun92...
**Support Chips:
**HT44          Secondary Cache                                c:Jun92...
**Other:...
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*Unresearched:...
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*ZyMOS...
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