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**93C488         5x86/486 Single Chip PCI controller            <Aug96
***Info:
ALD93C488 is  the worlds  first single chip  486/5x86 core  logic that
supports  Pipeline  Burst/Burst (PB)  Synchronous  SRAM  for L2  cache
implementation.   This  innovative feature  results  in much  superior
performance than  the previous generation core logic  design that uses
Asynchronous SRAM  for L2  cache. ALD93C488 also  features one  of the
highest integration in  the market and requires only  DRAM, BIOS and 9
pieces TTL  to complete a cost-effective PCI/ISA  system that supports
all available 486 pinout CPUs up to bus speed of 50 MHz.

Employing  state-of-the-art  0.6  Micron  CMOS  technology,  ALD93C488
integrates the  PB Cache  Controller, DRAM Controller,  ISA Peripheral
Controllers  ( Interrupt  Controller,  DMA Controller,  Timer/Counter,
Real-time Clock and  Keyboard Controller ), PCI and  ISA Interface and
an Enhanced Local Bus IDE Interface  into a single 208 QFP ( Quad Flat
Pack ) IC.

Applying  the same  technique as  the latest  Pentium systems,  the PB
Cache  Controller achieves  3,1,1,1  burst cycle  with Pipeline  Burst
Synchronous SRAM. Write  Back Cache Policy is employed  for better CPU
bandwidth utilization. Cache  size can range from 128 KB  to 1 MB. The
DRAM  Controller supports  Page, Fast  Page and  EDO DRAM  for maximum
compatibility and ultimate performance. Four  banks of DRAM, from 1 MB
to 256  MB, can  be accessed, with  Auto-detection of memory  type and
size.

The  PCI Interface meets  the requirements  of PCI  Specifications 2.1
(5V). To  support PCI cards  that have on-board intelligence,  two PCI
Bus Masters can  be used.  In addition to  Host-to-PCI Byte Merging, a
4-level Host-to-PCI Write Buffer  is designed to ensure maximum system
throughput.  The built-in Enhanced Local Bus IDE Interface supports up
to 4 IDE devices (PIO  Mode 4 timing).  Advanced features like Address
Swapping  between  Primary  and   Secondary  IDE  Ports  and  separate
Master/Slave modes are implemented.  To make computers environmentally
friendly,  ALD93C488  is  equipped  with integrated  power  management
technique to stop or slow down the CPU.

***Configurations:...
***Features:...
*ALi...
*AMD . . . . . . . [no datasheets, some info]...
*Chips & Technologies...
*Contaq  . . . . . [no datasheets, some info]...
*Efar Microsystems [no datasheets, some info]...
*ETEQ...
*Faraday...
*Forex . . . . . . [List only, no datasheets found]...
*Intel...
**82495XP/490XP Cache Controller / Cache RAM (for i860)       06/05/91
***Notes:...
***Info:...
***Features:...
**82496/491     Cache Controller / Cache RAM (for P5 Pentium) 03/22/93...
**82497/492   Cache Controller / Cache RAM (for P54 Pentium)    <Nov94...
**82498/493   Cache Controller / Cache RAM (for P54 Pentium)    <Nov94...
**
**Later chipsets (basic spec):
**440 series:...
**450NX  (?)            06/29/98:...
**?????  (Profusion)    c:99...
**800 series...
*Headland/G2...
*HMC (Hulon Microelectronics)...
*Logicstar...
*Motorola...
*OPTi...
**82C701         FireStar Plus                                    c:97
***Notes:...
***Info:
Overview
This section  describes the follow-on  chip to the OPTi  FireStar ACPI
solution, the FireStar Plus.  The key features of this new product can
be summarized as follows.

o   Mostly  backward-compatible in pin function and register set with 
    FireStar ACPI (some PIO functions have been moved from critical 
    pins to improve timing)
o   Implements ATA-33 (Ultra DMA) IDE Interface, with support for all 
    modes
o   Supports 2.5V CPUs
o   Incorporates MA13 support for 64Mb SDRAM chips
o   Incorporates 64Mb EDO DRAM support
o   Enables use of synchronous DRAM on all six banks (original 
    FireStar chip limited synchronous DRAM to the first four banks)
o   Allows redefinition of many interface pins for better utilization 
    of chipset PIO features (many new function pins are easily 
    available)

Features
The  following paragraphs  describe  the feature  set changes  between
FireStar ACPI and FireStar Plus.

Ultra DMA IDE Interface
The ATA33 specification for  synchronous bus mastering IDE, also known
as Ultra DMA, is fully supported by FireStar Plus.

Synchronous DRAM on All Banks 
The original FireStar chip  supports synchronous DRAM only on RAS0-3#.
FireStar  Plus  also  supports   synchronous  DRAM  on  RAS4-5#.   The
additional functionality  is selected  through register bits  that are
already defined on the FireStar ACPI part.

2.5V CPU Interface 
FireStar Plus supports newer CPUs with I/O voltage requirements as low
as 2.5V.  The pin redefinition is as follows.
o   Pins E8, G5, T5, and W5 are now VCC_CPU and can be powered at 2.5V 
    or 3.3V.  
o   Pins K5, H22, and AB19 are now VCC_CORE and must always be powered 
    at 3.3V.  
o   Pin M5, CPUCLKIN, must receive a clock on the VCC_CPU plane. So if 
    a 2.5V CPU is used, this clock should also be 2.5V.  

The 2.5V  interface is a strap-selected  option.  It is selected  by a
strap on pin B7 (new MA13 pin).  If B7 is sensed low at reset, the CPU
interface is  3.3V; if sensed high  along with TMS (pin  AB5) low, the
CPU interface is 2.5V.

Redefinition of DRQ/DACK# Interface
The 7  pins assigned  to DACK0-7# can  be redefined to  improve avail-
ability of PIO pins.

While the  new definition only  involves circuit modifications  to the
DACK0-7# pins,  the overall  gain is much  greater when used  with the
82C602A Companion Chip in its Viper Note-book Mode A configuration.

o   8 power management inputs are now available, muxed in with the 
    DRQs and IRQ8# on the four EPMMUX pins.  
o   7 full-featured PIO pins are available on the former FireStar 
    DRQ0-7 pins and IRQ8# pin. The number of pins is actually 8, but 
    is reduced b y 1 because one must be programmed as ATCLK/2.   
o   12 PPWR outputs are generated by latching the SD bus lines from 
    PCTLH (FireStar PPWRL) and PCTLL (FireStar RSTDRV).
o   The ISA bus RSTDRV signal is now generated by the 82C602A chip, so 
    that the FireStar RSTDRV pin can be used for PPWR generation 
    (power control latch control signal). If the extra PPWR signals 
    are not needed, the FireStar RSTDRV pin becomes useful as a full-
    featured PIO pin.

Warnings 
1.  Until the Extended Mode  option has been programmed, DACK3-7# will
be  driving out  against  the  signal input  muxes.   It is  therefore
important  to  ensure  that the  logic  will  not  be harmed  by  this
arrangement  (the  FireStar  outputs  safely accept  being  driven  by
external logic in this mode).

2.  EDACKEN is  an option used to ensure  proper ISA master operation.
It prevents the EDACK decoder  from glitching its DACK# outputs during
EDACK switching.  If ISA masters are not supported in the system, this
option is not needed (tie the EDACK line high on the 82C602A).

3.  There are  no provisions to block conflicts in  case more than one
pin is programmed to the same  function.  For example, if a PIO pin is
programmed to be  ACPI8-11, and the Extended Mode  option also enables
EPMMUX1 to bring in ACPI8-11, the results are unpredictable.

***Configurations:...
***Features:...
**82C750         Vendetta      [no datasheet]                        ?...
**82c801         SCWB2 DX Single Chip Solution                    c:92...
**82C802         SCWB2 PC/AT Single Chip [no datasheet]              ?...
**82C802G/GP     System/Power Management Controller (cached)      c:93...
**82C895         System/Power Management Controller (cached)   c:Sep94...
**82C898         System/Power Management Controller (non-cache)c:Nov94...
**
**Support Chips:
**82C601/2       Buffer Devices                                 <Nov94...
**82C822         PCIB (VLB-to-PCI bridge)                         c:94...
**Other:...
*PC CHIPS/Amptron/Atrend/ECS/Elpina/etc...
*SIS...
*Symphony...
*TI (Texas Instruments)...
*UMC...
*Unresearched:...
*VIA...
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*Winbond...
*ZyMOS...
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