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**93C488         5x86/486 Single Chip PCI controller            <Aug96
***Info:...
***Configurations:...
***Features:...
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**450NX  (?)            06/29/98:
Chips:
[82454NX] (PXB) [82453NX] (MUX) 
[82452NX] (RCG) [82451NX] (MIOC) 
[82371EB] (PIIX4E),                            
CPUs:          Single/Dual/Quad P-II Xeon/P-III Xeon
DRAM Types:    FPM EDO 2-way Interleave 4-way Interleave
Mem Rows:      8
DRAM Density:  16Mbit 64Mbit
Max Mem:       8GB
ECC/Parity:    Both
AGP speed:     N/A
Bus Speed:     100
PCI Clock/Bus: 1/3


**?????  (Profusion)    c:99...
**800 series...
*Headland/G2...
**HT25          3-volt Core Logic for 386SX                    c:Dec92
***Info:
The HT25  is the industry’s first  3-Volt single chip  core logic with
integrated  power management  for  386SX based  3-Volt systems.   Pro-
grammable  power  management features  give  system manufacturers  the
flexibility of offering customized system solutions.

GENERAL DESCRIPTION
The HT25 is a  PC/AT1M compatible single-chip solution with integrated
power management  designed to operate in a  3-Volt system environment.
This highly integrated chip facilitates  the design of low power, high
performance portable systems.  The  HT25 supports 3-Volt 386SX CPUs at
clock  speeds  up  to  25MHz  at  2.7V to  3.6V.   It  supports  power
management functions using the System Management Mode (SMM).

Flexible  power  management is  the  cornerstone  of the  HT25.   This
approach provides  power saving  features that  can be  customized for
product  differentiation.  Power  management  features include  system
activity monitors  and general purpose  I/O pins.  The  HT25 generates
System Management  Interrupt (SMI) to process  activity information or
when access  to powered down  peripherals is detected.   Further power
savings are achieved through the HT25’s ability to control CPU and NPU
clocks and support for slow refresh and self refresh DRAMs.

The HT25 Memory Controller features BIOS Shadowing, Memory Relocation,
EMS, Page  Mode Memory Access and Interleaving.  The memory controller
allows memory banks to be reordered to allow more efficient memory in-
terleaving. The HT25 supports 512Kb, le, and 4Mb DRAMs.

The HT25 architecture  is optimized for 3-Volt system  designs, the SD
bus acknowledge input provides a flexible I/O bus architecture and the
XD bus is buffered directly  from the HT25.  Further, no external data
bus buffers are required for a closed 3V system.

***Configurations:...
***Features:...
**HT35          Single-Chip Peripheral Controller [partial info]     ?...
**HTK320        386DX Chip Set                                 c:Sep91...
**HTK340        "Shasta" 486 Chip Set                          c:Jun92...
**Support Chips:
**HT44          Secondary Cache                                c:Jun92...
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