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**82380FB/AB PCIset: 82380FB Mobile PCI-to-PCI Bridge(MPCI2) 02/17/97
***Notes:...
***Info:...
***Versions:...
***Features:...
**82384 Clock Generator and Reset Interface c86...
**82385 32-bit Cache Controller for 80386 09/29/87...
**82385SX 32-bit Cache Controller for 80386SX 01/25/89...
**82395DX High Performance Smart Cache 06/18/90...
**82395SX Smart Cache 12/17/90...
**82396SX Smart Cache 12/17/90...
**82485 Turbo Cache (and 485Turbocache) c90...
**82489DX Advanced Programmable Interrupt Controller 10/12/92
***Notes:...
***Info:
1.0 INTRODUCTION
The 82489DX Advanced Programmable Interrupt Controller provides
multiprocessor interrupt management, providing both static and dynamic
symmetrical interrupt distribution across all processors.
The main function of the 82489DX is to provide interrupt management
across all processors. This dynamic interrupt distribution includes
routing of the interrupt to the lowest-priority processor. The 82489DX
works in systems with multiple I/O subsystems, where each subsystem
can have its own set of interrupts. This chip also provides
inter-processor interrupts, allowing any processor to interrupt any
processor or set of processor. Each 82489DX I/O init interrupt input
pin is individually programmable by software as either edge or level
triggered. The interrupt vector and interrupt steering information an
be specified per pin. A 32-bit wide timer is provided that can be
programmed to interrupt the local processor. the timer can be used as
a counter to provide a time base to software running on the processor,
or to generate time slice interrupts locally to that processor. the
82489DX provides 32-bit software access to its internal
registers. Since no 82489DX register read have any side effects, the
82489DX registers can be aliased to a user read-only page for fast
user access (e.g., performance monitoring timers).
The 82489DX supports a generalized naming/addressing scheme that can
be tailored by software to fit a variety of system architectures and
usage models. It also supports 8259A compatibility by becoming
virtually transparent with regard to an externally connected 8259A
style controller, making the 8259A visible to software.
***Versions:...
***Features:...
**82495DX/490DX DX CPU-Cache Chip Set <Sep91...
**82495XP/490XP Cache Controller / Cache RAM (for i860) 06/05/91...
**82496/491 Cache Controller / Cache RAM (for P5 Pentium) 03/22/93...
**82497/492 Cache Controller / Cache RAM (for P54 Pentium) <Nov94...
**82498/493 Cache Controller / Cache RAM (for P54 Pentium) <Nov94...
**
**Later chipsets (basic spec):
**440 series:...
**450NX (?) 06/29/98:...
**????? (Profusion) c:99...
**800 series...
*Headland/G2...
*HMC (Hulon Microelectronics)...
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*OPTi...
*PC CHIPS/Amptron/Atrend/ECS/Elpina/etc...
*SIS...
*Symphony...
*TI (Texas Instruments)...
*UMC...
**UM82C230 286AT MORTAR Chip Set <91
***Info:
The UMC's MORTAR (286AT) Chip Set UM82C230 series provides an economic
alternative for building a reliable IBM PC/AT compatible system. A
commercial 12MHZ/0 wait state, 4MByte main memory system and
math-coprocessor can be easily built by using 3 VLSIs, 8 logic
components plus memory and processor.
The UM82C230 MORTAR chipset consists of the UM82C231 System/Memory
Controller, the UM82C232 Data/Address Buffer and the UM82C206
Integrated Peripherals Controller (IPC).
As shown in the System Block Diagram, [see datasheet] there are three
data buses: local data bus, AT data bus and peripheral data (XD) bus.
The local DRAM, EPROM and Numerical Processor are located on the local
data bus. The UM82C206 and 8042 Keyboard Controller sit on the XD bus.
The AT data bus was driven by the UM82C232 directly which conveys the
data to/from the AT Channel Adaptors.
The address bus architecture is also very simple; local CPU address
bus, local DRAM address bus (MA), peripheral address bus (XA) and AT
address bus. The local address bus is shared between CPU, UM82C231 and
UM82C206. The MA bus is used by the local DRAM only. Most of the
system board devices are attached to the XA bus, like UM82C232,
UM82C206, ROMs and 8042. Some AT address lines are driven by the
UM82C231 or UM82C232 directly; the others are buffered.
The UM82C231 provides synchronization and control signals for all
buses. The UM82C231 also distinguishes if the current cycle is local
memory cycle. Upon detecting that it is a local DRAM cycle, no AT
control signals are sent out to the AT channel. The UM82C231 is based
on the memory configurations to complete the current cycle with
fastest response. If the cycle is AT cycle, the UM82C231 sends out the
control signals sequentially which are then used by the adaptors or
system board devices to receive the write data or to send the fetched
data. Then, depending on the status signals sent back by the adaptors
or system board devices, the UM82C231 determines which kind of AT
cycles to perform: 8-bit, 16-bit, bus conversion, wait state insert,
or wait state cycle.
The UM82C232 Data/Address buffer provides the buffering and latching
between the CPU local data bus, AT bus and XD bus. The parity bit
generation and parity bit checking logic resides in the UM82C232 also.
During DMA cycles, the UM82C232 latches the address from XD, which is
sent by the UM82C206, and transfers to XA bus.
***Configurations:...
***Features:...
**UM82C210 386SX/286 AT Chip Set <91...
**UM82C3xx Twinstar & UM82C336F/N & UM82C39x [no datasheet] ?...
**UM82C380 386 HEAT PC/AT Chip Set <91...
**UM82C480 386/486 PC Chip Set c91...
**UM82C493/491 ??????????????? [no datasheet] ?...
**UM8498/8496 486 VL Chipset "Super Energy Star Green"[no dsheet]c94...
**UM8881/8886 HB4 PCI Chipset "Super Energy Star Green"[no dsheet]c94...
**UM8890 Pentium chipset [no datasheet] ?...
**
**Support Chips:
**UM82152 Cache Controller (AUStek A38152 clone) <91...
**UM82C852 Multi I/O For XT <91...
**UM82C206 Integrated Peripheral Controller <91...
**UM82c45x Serial/Parallel chips ?...
**Other chips:...
*Unresearched:...
*VIA...
*VLSI...
*Western Digital...
*Winbond...
*ZyMOS...
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