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**82380       32-bit DMA Controller w/ Integrated Peripherals 02/01/87
***Notes:...
***Info: 
The  82380  is a  multi-function  support  peripheral that  integrates
system  functions necessary  in  an 80386  environment.  It has  eight
channels  of  high performance  32-bit  DMA  with  the most  efficient
transfer rates  possible on the 80386 bus.  System support peripherals
integrated  into the  82380  provide Interrupt  Control, Timers,  Wait
State generation, DRAM Refresh Control, and System Reset logic.

The  82380's  DMA Controller  can  transfer  data  between devices  of
different data  path widths using  a single channel. Each  DMA channel
operates independently  in any of  several modes.  Each channel  has a
temp orary data storage register for handling non-aligned data without
the need for external alignment logic.

The 82380 contains several  independent functional modules.  The foll-
owing  is a brief  discussion of  the components  and features  of the
82380. E$ch module has a  corresponding detailed section later in this
data  sheet.  Those  sections should  be  referred to  for design  and
programming information.

82380 Architecture:

The 82380 is  comprised of several computer system  functions that are
normally found in separate LSI  and VLSI components.  These include: a
high-performance,  eight-channel, 32-bit  Direct  Memory Access  Cont-
roller; a 20-level Programmable Interrupt Controller which is a super-
set of the 82C59A; four  16-bit Programmable Interval Timers which are
functionally  equivalent to  the 82C54  timers; a  DRAM  Refresh Cont-
roller;  a  Programmable  Wait   State  Generator;  and  system  reset
logic. The  interface to the  82380 is optimized  for high-performance
operation with the 80386 microprocessor.

The 82380  operates directly on the  80386 bus. In the  Slave mode, it
monitors the  state of the  processor at all  times and acts  or idles
according  to  the commands  of  the  host.  It monitors  the  address
pipeline status·. and  generates the programmed number  of wait states
for the device  being accessed. The 82380 also has  logic to reset the
80386 via hardware  or software reset requests  and processor shutdown
status.

After a  system reset, the 82380 is  in the Slave mode.  It appears to
the  system as  an I/O  device. It  becomes a  bus master  when  it is
performing DMA transfers.

To maintain compatibility with existing software, the registers within
the 82380  are accessed as bytes.  If the internal logic  of the 82380
requires a delay  before another access by the  processor, wait states
are  automatically inserted into  the access  cycle.  This  allows the
programmer to  write initialization  routines, etc. without  regard to
hardware recovery times.
***Versions:...
***Features:...
**82380FB/AB  PCIset: 82380FB Mobile PCI-to-PCI Bridge(MPCI2) 02/17/97...
**82384       Clock Generator and Reset Interface                  c86...
**82385       32-bit Cache Controller for 80386               09/29/87...
**82385SX     32-bit Cache Controller for 80386SX             01/25/89...
**82395DX     High Performance Smart Cache                    06/18/90...
**82395SX     Smart Cache                                     12/17/90...
**82396SX     Smart Cache                                     12/17/90...
**82485       Turbo Cache (and 485Turbocache)                      c90...
**82489DX       Advanced Programmable Interrupt Controller    10/12/92...
**82495DX/490DX DX CPU-Cache Chip Set                           <Sep91
***Notes:...
***Info:...
***Configurations:...
***Features:...
**82495XP/490XP Cache Controller / Cache RAM (for i860)       06/05/91...
**82496/491     Cache Controller / Cache RAM (for P5 Pentium) 03/22/93
***Notes:...
***Info:...
***Configurations:...
***Features:...
**82497/492   Cache Controller / Cache RAM (for P54 Pentium)    <Nov94...
**82498/493   Cache Controller / Cache RAM (for P54 Pentium)    <Nov94...
**
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