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**82378 System I/O (SIO) (82378IB and 82378ZB) c:Mar93
***Notes:...
***Info:
****All...
****Oct'93...
****Dec'94...
****All...
****Mar'93...
****Dec'94...
****All:
The arbiter can be programmed for a purely
rotating scheme, fixed, or a combination of the two. The Arbiter can
also be programmed to support bus parking. This gives the Host Bridge
default access to the PCI bus when no other device is requesting
service. The arbiter can be disabled if an external arbiter is used.
PCI Decode/ISA Decode:
The SIO contains two address decoders; one to decode PCI initiated
cycles and one to decode ISA master and DMA initiated cycles. Two
decoders are used to allow the PCI and ISA busses to run concurrently.
The SIO is also programmable to provide address decode on behalf of
the Host Bridge. When programmed, the SIO monitors the PCI and ISA
address busses, and generates a memory chip select signal (MEMCS#)
indicating that the current cycle is targeted for system memory
residing behind the Host Bridge. This feature can be disabled through
software.
Data Buffers:
To isolate the slower ISA bus from the PCI bus, the SIO provides two
types of data buffers. One Dword deep posted write buffer is provided
for the posting of PCI initiated memory write cycles to the ISA bus.
The second buffer is a bi-directional, 8 byte line buffer used for ISA
master and DMA accesses to the PCI bus. All DMA and ISA master read
and write cycles go through the 8 byte line buffer.
The data buffers also provide the data assembly or disassembly when
needed for transactions between the PCI and ISA busses.
Buffering is programmable and can be enabled or disabled through
software.
ISA Bus Interface:
The SIO incorporates a fully ISA-bus compatible master and slave
interface. The SIO directly drives six ISA slots without external data
or address buffering. The ISA interface also provides byte swap
logic, I/O recovery support, wait-state generation, and SYSCLK
generation. The SIO supports ISA bus frequencies from 6 to B.33 Mhz.
As an ISA master, the SIO generates cycles on behalf of DMA, Refresh,
and PCI master initiated cycles. The SIO supports compressed cycles
when accessing ISA slaves (ie. ZEROWS# asserted). As an ISA slave, the
SIO accepts ISA master accesses targeted for the SIO's internal
register set or ISA master memory cycles targeted for the PCI bus. The
SIO does not support ISA master initiated I/O cycles targeted for the
PCI bus.
The SIO also monitors ISA master to ISA slave cycles to generate
SMEMR# or SMEMW#, and to support data byte swapping, if necessary.
DMA:
The DMA controller incorporates the functionality of two 82C37 DMA
controllers with seven independently programmable channels. Each
channel can be programmed for 8-bit or 16-bit DMA device size, and
ISA-compatible or fast DMA type "A", type "B", or type F"
timings. Full 32-bit addressing is supported as an extension of the
ISA-compatible specification. The DMA controller is also responsible
for generating ISA refresh cycles.
The DMA controller supports an enhanced feature called Scatter/
Gather. This feature provides the capability of transferring multiple
buffers between memory and I/O without CPU intervention. In Scatter/
Gather mode, the DMA can read the memory address and word count from
an array of buffer descriptors, located in system memory, called the
Scatter/Gather Descriptor (SGD) Table. This allows the DMA controller
to sustain DMA transfers until all of the buffers in the SGD table are
read.
Timer Block:
The timer block contains three counters that are equivalent in
function to those found in one 82C54 programmable interval
timer. These three counters are combined to provide the System Timer
function, Refresh Request, and speaker tone. The three counters use
the 14.31818 Mhz OSC input for a clock source.
In addition to the three counters, the SIO provides a programmable
16-bit BIOS timer. This timer can be used by BIOS software to
implement timing loops. The timer uses the ISA system clock (SYSCLK)
divided by 8 as a clock source. An 8 to 1 ratio between the SYSCLK and
the BIOS timer clock is always maintained. The accuracy of the BIOS
timer is ± 1 msec.
Utility Bus (X-Bus) Logic:
The SIO provides four encoded chip selects that are decoded externally
to provide chip selects for Flash BIOS, Real Time Clock,
Keyboard/Mouse Controller, Floppy Controller, two Serial Ports, one
Parallel Port, and an IDE Hard Disk Drive. The SIO provides the
control for the buffer that isolates the lower 8-bits of the Utility
Bus from the lower 8-bits of the ISA bus.
In addition to providing the encoded chip selects and Utility Bus
buffer control, the SIO also provides Port 92 functions (Alternate
Reset and Alternate A20), Coprocessor error reporting, the Floppy
DSKCHG function, and a mouse interrupt input.
Interrupt Controller Block:
The SIO provides an ISA compatible interrupt controller that incor-
porates the functionality of two 82C59 interrupt controllers. The two
interrupt controllers are cascaded so that 14 external and two
internal interrupts are possible.
Test:
The test block provides the interface to the test circuitry within the
SIO. The Test input can be used to tri-state all of the SIO outputs.
***Versions:...
***Features:...
**82379AB System I/O-APIC (SIO.A) <Dec94...
**82380 32-bit DMA Controller w/ Integrated Peripherals 02/01/87...
**82380FB/AB PCIset: 82380FB Mobile PCI-to-PCI Bridge(MPCI2) 02/17/97...
**82384 Clock Generator and Reset Interface c86...
**82385 32-bit Cache Controller for 80386 09/29/87...
**82385SX 32-bit Cache Controller for 80386SX 01/25/89...
**82395DX High Performance Smart Cache 06/18/90...
**82395SX Smart Cache 12/17/90...
**82396SX Smart Cache 12/17/90...
**82485 Turbo Cache (and 485Turbocache) c90...
**82489DX Advanced Programmable Interrupt Controller 10/12/92...
**82495DX/490DX DX CPU-Cache Chip Set <Sep91...
**82495XP/490XP Cache Controller / Cache RAM (for i860) 06/05/91
***Notes:...
***Info:...
***Features:...
**82496/491 Cache Controller / Cache RAM (for P5 Pentium) 03/22/93...
**82497/492 Cache Controller / Cache RAM (for P54 Pentium) <Nov94...
**82498/493 Cache Controller / Cache RAM (for P54 Pentium) <Nov94...
**
**Later chipsets (basic spec):
**440 series:...
**450NX (?) 06/29/98:...
**????? (Profusion) c:99...
**800 series...
*Headland/G2...
*HMC (Hulon Microelectronics)...
*Logicstar...
*Motorola...
*OPTi...
**82C391/392 386WB PC/AT Chipset (386DX) <Dec90
***Info:...
***Configurations:...
***Features:...
**82C461/462 Notebook PC/AT chipset [no datasheet] ?...
**82c463 SCNB Single Ship Notebook c:92...
**82c465MV/A/B Single-Chip Mixed Voltage Notebook Solution <Oct97...
**82C481?/482? HiP/486 & HiB/486 [no datasheet] Oct89...
**82C491/392 486WB PC/AT Chipset <04/21/91...
**82C493/392 486SXWB <10/21/91...
**82C495SX/392SX LCWB PC/AT chipset [no datasheet] ?...
**82C495SLC DXSLC 386/486 Low Cost Write Back c:92...
**82C495XLC PC/AT Chip Set c:93...
**82c496A/B DXBB PC/AT Chipset <Mar92...
**82C496/7 DXBB PC/AT Chipset (Cached) <01/16/92...
**82C498 DXWB PC/AT chipset [no datasheet] ?...
**82C499 DXSC DX System Controller c:93...
**82C546/547 Python PTM3V c:94...
**82C556/7/8 Viper [no datasheet] ?...
**82C556/7/8N Viper-N Viper Notebook Chipset <05/25/95...
**82C556M/7M/8E Viper-N+ Viper Notebook Chipset c:96...
**82C566/7/8 Viper-Max Chipset Scalable MultiMedia PC Solution ?...
**82C571/572 486/Pentium c:93...
**82C576/7/8 Viper Xpress [no datasheet] ?...
**82C576/8/9 Viper XPress+ [no datasheet, some info] <01/16/97...
**82C596/597 PTMAWB Pentium Adaptive Write-back (Cobra) c:93...
**82C650/1/2 Discovery (Pentium Pro) [no datasheet] ?...
**82C681/2/6/7 386/486WB EISA c:92...
**82C683 386/486AWB EISA [no datasheet] ?...
**82C693/6/7 Pentium uP Write Back Cache EISA c:93...
**82C700 FireStar c:97...
**82C701 FireStar Plus c:97...
**82C750 Vendetta [no datasheet] ?...
**82c801 SCWB2 DX Single Chip Solution c:92...
**82C802 SCWB2 PC/AT Single Chip [no datasheet] ?...
**82C802G/GP System/Power Management Controller (cached) c:93...
**82C895 System/Power Management Controller (cached) c:Sep94...
**82C898 System/Power Management Controller (non-cache)c:Nov94...
**
**Support Chips:
**82C601/2 Buffer Devices <Nov94...
**82C822 PCIB (VLB-to-PCI bridge) c:94...
**Other:...
*PC CHIPS/Amptron/Atrend/ECS/Elpina/etc...
*SIS...
*Symphony...
*TI (Texas Instruments)...
*UMC...
*Unresearched:...
*VIA...
*VLSI...
*Western Digital...
*Winbond...
*ZyMOS...
*General Sources:...
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