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*ACC Micro...
**ACC2087    Enhanced Super Chip (486 Single Chip)              <Aug96
***Info:
[no general description]

[below is *selected* parts of the functional description]

The  ACC2087  supports the  486  and  386DX  CPUs. The  CPU  interface
selection is determined  by detecting a pull up  or pull down resistor
on pin 172  (M486) during the reset period. A pull  up resistor on pin
172 will  trigger the ACC2087 operating  in the 486 mode.  A pull down
resistor on  pin 172 will trigger  the ACC2087 operating  in the 386DX
mode.

80387 Interface Control:
The 80387  interfaces directly to  the 386DX with  the error-reporting
logic  built  in the  ACC2087.  A coprocessor  error  is  sent to  the
ACC2087, generating  an interrupt  request to the  CPU, followed  by a
service  request. A write  operation to  I/O port  0F0 will  clear the
interrupt request.

Clock Throttling:
To further  reduce the power  consumption in the Notebook  system, the
ACC2087 supports  another mode called Clock  Throttling. After scaling
the CPU clock, the ACC2087 can periodically assert the STPCLK# request
which will  force the CPU into  Stop Grant State. Hence  the CPU power
can be further reduced.

Local Bus Peripheral Support Master / DMA Mode and SMM Support in 
Local Bus Cycle:
The  ACC2087 supports  VL-Bus with  master and  DMA modes.  To further
enhance the  flexibility, the local  bus can be detected  under System
Management Mode (SMM).

Intel System Management Mode Interface (SMM)
System Management  Mode (SMM) is  designed to handle  power management
interrupts  that are  totally  transparent to  the existing  programs,
operating  systems  and  CPU  operation modes.  The  ACC2087  contains
dedicated  logic  to  interface  with  SMM implemented  by  the  Intel
SL-enhanced  486 for battery-powered  portable computers.  The ACC2087
utilizes the  DRAMs located  between segments A000h  and B000h  as the
separate SMM memory (SMRAM) required by SMM functions.

Power Management Features:
The ACC2087  provides a powerful mechanism of  system power management
that is completely transparent to the operating system and application
software.  It was  designed from  the system  level to  synthesize and
manage  power  consumption  for   the  lowest  power  operation  while
maintaining system performance in the portable system.

High Performance Cache Controller:
The integrated ACC2087 cache controller supports a direct mapped cache
from 32 Kbytes up to 2  Mbytes in size. The direct mapped architecture
means that a specified line in  the cache is capable of caching only a
certain range of  memory addresses. The low order  address bits choose
the location (index) while the  high order address bits (tag) identify
the entry.

As  for write  policy, the  ACC2087 supports  either write  through or
write  back  cache implementations.  In  addition,  the ACC2087  cache
architecture can  be used  in both 386DX  and 486 applications.  For a
386DX design,  the ACC2087 cache controller  can be used  to support a
primary cache. In a 486 AT system, if the internal cache of the 486 is
enabled,  the ACC2087  direct mapped  cache can  be used  as secondary
cache.

Memory Controller:
The Memory Controller is a  key feature of the ACC2087. This versatile
circuit  provides complete  control of  up to  64 megabytes  of system
DRAM. In any control mode, it generates up to four Row Address Strobes
(RAS#0-3)  and  one Memory  Write  Enable  signal  (WEN#). The  Memory
Controller also  provides the interface  to transfer control to  a DMA
controller or an AT Bus master.

The ACC2087 Memory Controller supports  256KB, 512KB, 1MB and 4MB DRAM
devices.  The ACC2087  provides all  control signals  and programmable
control  to  support  256Kx1,   512Kx1,  1Mx1,  1Mx4,  4Mx1  and  4Mx4
(symmetrical only).

Memory Mapping:
Memory Mapping translates  system RAM within the 640  KB to 1MB range,
which  is reserved  for the  system ROM  and BIOS  application,  to an
accessible address range above the physical RAM space. For example, if
4 MB  of memory are installed,  and the memory mapping  feature is on,
the  DRAMs in  the  640  KB to  1MB  range are  mapped  to an  address
immediately above 4 MB.

Shadow RAM
Shadow RAM provides an option to transfer BIOS or video-extension BIOS
program  codes  into system  RAM.   This  option provides  significant
performance  improvement  for  applications requiring  intensive  BIOS
calls.

Shadow RAM implements an alternate BIOS source by copying the complete
EPROM program code into system RAM. This is referred to as "shadowing"
because  the DRAM  and EPROM  are both  located in  the  same physical
address  space.  This  change  is  transparent  to  the  rest  of  the
system. ROM can  then be disabled, allowing the RAM  to respond in its
place.

Interrupt Controllers
There are two programmable interrupt controllers for the ACC2087. They
are fully compatible with Intel's  8259 controller, providing up to 15
interrupt  sources (14  external and  1 internal).  The  internal line
connects to the 8254 Counter 0 output.

These interrupt controllers prioritize interrupt requests to the CPU.

DMA
The ACC2087 has  two DMA controllers, compatible with  the Intel 8237,
which provide a total of seven external DMA channels.

Combined with the Memory Mapper, each DMA channel has a 24-bit address
output to access data throughout the 64 megabyte system address space.

Memory Mapper
The ACC2087 has a built-in logic equivalent to the 74LS612, generating
the upper address bits during a DMA cycle.

Timer/Counter
The  ACC2087 provides  three internal  counters, which  are compatible
with the 8254. The clock input for  each counter is tied to a clock of
1.19 MHz, which is derived by dividing the 14.318 MHz crystal input by
12.  The  output of  Counter  0  is connected  to  the  IRQ0 input  of
interrupt  controller  1. Counter  1  initiates  a  refresh cycle  and
Counter 2 generates sound waveforms for the speaker.

ACC2087 I/O Address Map
The ACC2087  I/O address decode is  fully compatible to  the IBM PC/AT
requirements. The ACC2087  has decoded the I/O address  range from 000
to 0FF to allow users to use the I/O areas not used by the IBM PC/AT.

PIO
The PIO  is the system configuration  to control the  speaker port. It
also has circuitry to detect  refresh. This condition can be read back
as Bit 4 of I/O Port 61h.

DMA Arbitration Logic
There are two  possible sources for a hold request  to the CPU. Either
the DMA controller issues a hold request or the output of Counter 1 in
the 8254 makes a low to  high transition. The HOLD line is active when
either source is requesting a  hold. The ACC2087 contains the logic to
do the arbitration.

Refresh Generation Logic
The ACC2087 contains circuitry  to perform DRAM refresh cycle. Refresh
circuitry  contains  an  8-bit  counter  for address  SA0-7  during  a
refresh. In  addition, three more  address counter bits  are presented
inside the ACC2087 to support refresh for DRAMs up to 4M bits.

Staggered Refresh Logic
The ACC2087 refresh logic works to perform a periodic refresh for both
system DRAM  and extended RAM on  the AT Bus. The  ACC2087 initiates a
refresh  cycle by  driving its  REFRESH# output  low, and  driving the
refresh address  onto the MA Bus,  simultaneously generating staggered
refresh pulses on the four RAS outputs.  The RAS outputs are staggered
to reduce  the current drain  caused by the refresh  operation. During
each  refresh cycle, the  ACC2087 drives  the current  refresh address
onto  the  AT address  bus.  This  provides  the refresh  address  for
extended memory.

NMI and Port B Logic
The  ACC2087 contains non-maskable  interrupt (NMI)  signal generation
logic. An NMI can be caused by an I/O error or by a parity error. Port
B identifies the  source of the error. At power up,  the NMI signal is
masked off.  NMI is enabled by writing  to I/O address 070  with bit 7
low; NMI is disabled by writing to I/O address 070 with bit 7 high.

Bus Controller and Converter
The flexible ACC2087 Bus Controller  provides all of the control logic
needed  to interface  to  the CPU,  alternate  masters, local  memory,
primary  or  secondary  cache and  the  AT  bus.  Each access  may  be
initiated by the ACC2087 decoding  the address and cycle type provided
on the local  CPU bus. The cycle type is  determined by monitoring the
signals D/-C, W/-R and M/-IO.

Turbo Speed Control Logic
The  CPU clock frequency  can be  switched between  CLKSRC and  the AT
clock. The  frequency switch can be generated  through either hardware
or software.  A TURBO pin is  provided to support a  front panel turbo
speed switch.  TURBO high selects CLKSRC  as the CPU  clock. TURBO low
selects AT Bus clock as the CPU clock.

For power  conservation, a standby  mode clock control is  provided. A
system needs to pre-select the standby frequency first, then BIOS will
monitor the activity  of the system. If all  pre-defined conditions of
the standby  mode are satisfied, the  system will go  into the standby
mode by  programming bit 3 of Register  8h to 1 or  if the Turbo/Sleep
bit has been set to 1. The  Turbo pin, when driven low, will force the
system into sleep mode.

OS/2 Optimization
The ACC2087  implements OS/2 optimization,  which is a  more efficient
way to  switch back and forth  between real and protected  modes in an
OS/2  environment  when  frequent  DOS calls  are  made.  Conventional
methods  require  the processor  to  communicate  with the  integrated
/external  keyboard  controller in  switching  to  protected mode  and
activating gate A20.

With  OS/2 optimization, the  ACC2087 allows  control of  software CPU
reset and A20 gating through Port 92h.

Floppy Disk Drives
With the  ACC2087, designers can build  an IBM PC/XT  or AT compatible
Floppy Disk Drive with fast access time, high reliability and low cost
per bit capability. The ACC2087 integrates the functions of a standard
floppy disk drive controller.

Data separator
Write precompensation circuit
Decode logic
Data rate selection
Clock generation
Drive interface drivers and receivers.

This integration greatly reduces  the number of components required to
interface floppy disk drives to a microprocessor system.

Serial Port Interface
The ACC2087 supports two NS16C550 compatible serial ports. Each serial
port interface  converts data from  peripheral devices or  modems from
serial-in-data to parallel-out-data. Data  transmitted from the CPU is
converted from parallel-in-data to  serial-out-data. The status of the
UART can  be read during any  CPU operation. Status  includes type and
condition  of   the  transfer   operations  in  progress,   and  error
conditions.

Parallel Port Interface
The parallel port interface  in the ACC2087 provides compatibility for
a  Centronics  type printer.  Its  configuration  register allows  the
parallel port  to be configured  in PS/2 type  bi-directional parallel
port and Extended Capabilities Port (ECP) modes. 


***Configurations:...
***Features:...
**ACC2089    486 PCI-based System Super Chip      [no datasheet]     ?...
**ACC2168/GT 32-bit 486 Green System Single Chip  [no datasheet]     ?...
**ACC2178A   32-bit 486 Green System Single Chip  [no datasheet]     ?
***Notes:...
***Info:...
***Configurations:...
**ACC2268    ?486                                 [no datasheet]     ?...
**ACC????    Maple/Maple-133 486-System-On-Chip   [no datasheet]     ?...
**
**Support Chips:
**ACC2016    Buffer and MUX Logic                                  c96...
**ACC2020    Power Management Chip                                 c92...
**ACC5500    Multifunction I/O Control Chip for PS2 Model 50/60    c88...
**
**Other chips...
*ALD...
*ALi...
*AMD . . . . . . . [no datasheets, some info]...
*Chips & Technologies...
*Contaq  . . . . . [no datasheets, some info]...
*Efar Microsystems [no datasheets, some info]...
*ETEQ...
*Faraday...
*Forex . . . . . . [List only, no datasheets found]...
*Intel...
**450NX  (?)            06/29/98:
Chips:
[82454NX] (PXB) [82453NX] (MUX) 
[82452NX] (RCG) [82451NX] (MIOC) 
[82371EB] (PIIX4E),                            
CPUs:          Single/Dual/Quad P-II Xeon/P-III Xeon
DRAM Types:    FPM EDO 2-way Interleave 4-way Interleave
Mem Rows:      8
DRAM Density:  16Mbit 64Mbit
Max Mem:       8GB
ECC/Parity:    Both
AGP speed:     N/A
Bus Speed:     100
PCI Clock/Bus: 1/3


**?????  (Profusion)    c:99...
**800 series...
*Headland/G2...
**GC101/102/103 12/16MHz PC/AT Compatible Chip Set + EMS 4.0   c:Jul89
***Notes:...
***Info:...
***Configurations:...
***Features:...
**GCK113        80386 AT Compatible Chip Set                   c:oct89...
**GCK181        Universal PS/2 Chip Set                        c:Mar89...
**HT11          Single 286 AT Chip [no datasheet]               <Aug90...
**HT12/+/A      Single 286 AT Chip with EMS support            c:Aug90...
**HT18          80386SX Single Chip                            c:Sep91...
**HT21          386SX/286 Single Chip (20 MHz)                 c:Aug91...
**HT22          386SX/286 Single Chip (25 MHz)                 c:Sep91...
**HT25          3-volt Core Logic for 386SX                    c:Dec92...
**HT35          Single-Chip Peripheral Controller [partial info]     ?...
**HTK320        386DX Chip Set                                 c:Sep91...
**HTK340        "Shasta" 486 Chip Set                          c:Jun92...
**Support Chips:
**HT44          Secondary Cache                                c:Jun92...
**Other:...
*HMC (Hulon Microelectronics)...
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*UMC...
*Unresearched:...
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*Western Digital...
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*ZyMOS...
*General Sources:...

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