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**82450KX/GX PCIset (Pentium Pro) KX/GX (Mars/Orion) 11/01/95
***Notes:...
***Info:
****General:...
****82454KX/GX PCI Bridge (PB):...
****Memory Controller (MC) 82453KX/GX (DC), 82452KX/GX (DP), 82451KX/GX (MIC)
The MC consists of the 82453KX/GX DRAM Controller (DC), the 82452KX/GX
Data Path (DP), and four 82451KX/GX Memory Interface Components
(MIC). The combined MC uses one physical load on the Pentium Pro
processor bus. The memory configuration can be either non-interleaved
(450KX/GX), 2-way interleaved (450KX/GX), or 4-way interleaved (450GX
only). Both single-sided and double-sided SIMMs are supported at 3.3
and 5 volts. DRAM technologies of 512kx8, 1Mx4, 2Mx8, 4Mx4, 8Mx8, and
16Mx4 at speeds of 50ns, 60ns, 70ns, and 80ns can be used. The maximum
memory size is 4 Gbytes for the 4-way interleaved configuration (450GX
only), 1 Gbyte (2 Gbytes for the 450GX) for the 2-way interleaved
configuration, and 512 Mbytes (1 Gbyte for the 450GX) for the
non-interleaved configuration. The MC provides data integrity
including ECC in the memory array, and parity on the host bus control
signals. The 450GX also provides ECC on the host data bus. The MC is
PC compatible. All ISA and EISA regions are decoded and shadowed based
on programmable configurations. Regions above 1 Mbyte with size 1
Mbyte or larger that are not mapped to memory may be reclaimed. Three
programmable memory gaps can be created. For the 450GX, two MCs can be
used in a system.
The Intel 450KX/GX PCIsets may contain design defects or errors known
as errata. Current characterized errata are available upon request.
----------------------------------------------------------------------
This document describes both the 82454KX and 82454GX
PCIsets. Unshaded areas describe features common to the 450KX and
450GX. Shaded areas, like this one, describe the 450GX operations
that differ from the 450KX.
----------------------------------------------------------------------
3.0 MC FUNCTIONAL DESCRIPTION
This section describes the MC functions and hardware interfaces
including the Memory and I/O Mapping, Host Bus Interface, DRAM
Interface, and Clocks and Reset.
3.1 Memory and I/O Map
The MC provides the interface between the host bus and main
memory. The processor memory space is 64 Gbytes (36-bit
addressing). An MC can control up to 1 Gbyte of memory for the 450KX
and 4 Gbytes of memory for the 450GX. The MC registers that control
memory space access are:
o Programmable Attribute Map (PAM[6:0]) Registers. These registers
provide Read Only, Write Only, and Read/Write Disable for fixed
memory regions in the PC compatibility area.
o Video Buffer Area Enable (VBA) Register. This register enables the
A0000–BFFFFh fixed region.
o Low Memory Gap (LMG) Register. This register defines a hole in
memory located from 1 to 4 Gbytes on any 1 Mbyte boundary where
accesses can be directed to the PCI bus (via the PB). The size can
be 1, 2, 4, 8, 16, or 32 Mbytes. This gap must be located below the
Memory Gap and High Memory Gap. The Low Memory Gap is used by ISA
devices such as LAN or linear frame buffers that are mapped into the
ISA Extended region, or by any EISA or PCI device.
o Memory Gap Registers (MG and MGUA) Registers. These two registers
define a hole in memory located from 1 to 64 Gbytes on any 1 Mbyte
boundary where accesses can be directed to the PCI bus (via the
PB). This gap (1, 2, 4, 8,16, or 32 Mbytes in size) must be located
above the Low Memory Gap and below the High Memory Gap areas. The
Memory Gap is used by ISA devices (e.g., LAN or linear frame
buffers) that are mapped into the ISA Extended region, or by any
EISA or PCI device.
o High Memory Gap Registers (HMGSA and HMGEA) Registers. These two
registers define a gap in memory that can be located from 1 to 64
Gbytes on any 1 Mbyte boundary where accesses can be directed to the
PCI bus (via the PB). The size ranges from 1 Mbyte to 64
Gbytes. This gap must be located above the Memory Gap and the Low
Memory Gap areas. The High Memory Gap provides additional support
for memory mapped I/O.
----------------------------------------------------------------------
• Base Address (BASEADD) Register. An 82453GX responds to memory
accesses between the address programmed into this register and the
calculated top of its memory range (calculated top of MC memory
address = base + memory size + Low Memory Gap size + Memory Gap
size + High Memory Gap size). Note that the DRAM memory behind the
memory gaps can be reclaimed.
----------------------------------------------------------------------
o SMMRAM Range (SMMR) Register and the SMMRAM Enable (SMME) Register
(Only when SMMEM# is asserted by the processor.). SM memory can
overlap with memory residing on the host bus or memory normally
residing on the PCI bus. When the SM range is enabled, SM accesses
are handled by the MC. If the SMMEM# signal is not asserted,
accesses to the MC’s enabled SM Range are ignored (this allows the
SM memory to overlap with memory normally residing on the host bus,
since the SMM Range may also be mapped through another MC range
register). The RSMI# signal may be asserted in the Response Phase by
a device in SMM power-down mode. The MC does not assert this signal.
o High BIOS (HBIOS) Register. The 64 Kbyte region from F0000–FFFFFh is
treated as a single block and is normally Read/Write disabled in the
MC(s) and Read/Write enabled in the PB. After power-on reset, this
region is R/W enabled in the PB (Compatibility PB only in the 450GX
and R/W disabled in the Auxiliary PB). Thus, the PB can respond to
fetches during system initialization. The Read/Write attributes for
this region may be used in conjunction with the Read/Write
attributes in the PB to "shadow" BIOS into RAM.
o I/O APIC Range (APICR) Register. This register provides an I/O APIC
configuration space. There is no I/O APIC in the PB or the MC.
o DRAM Row Limit (DRL) Registers. These registers define the upper and
lower addresses for each DRAM row and represent the boundary
addresses in 4 Mbyte granularity.
If a memory space access is in one of the above ranges, and that range
is enabled for memory access, the MC claims the transaction and
becomes the response agent.
The MC performs memory recovery on gap ranges greater than or equal to
1 Mbyte that are created by the Low Memory Gap, Memory Gap, and the
High Memory Gap areas. This memory is relocated to the top of the MC’s
memory. The MC performs a subtraction of the size of the hole in the
memory map to generate an effective memory address.
----------------------------------------------------------------------
For the 450GX, the base address for the MC that is not MC #0 must
include the size of any memory gaps programmed in the previous (or
lower base address) MC.
There can be up to two MCs in a system permitting up to 8 Gbytes of
system main memory. The portion of the processor’s memory space
controlled by an MC is determined by the Base Address Register and
memory size. In a PC architecture, the only restrictions on MC
placement are that there be memory starting at address 0 and that
there be enough memory to operate a system. The MCs in a system need
not have contiguous address spaces. The High Memory Gap in one MC
could be used to span the gap between the top of its memory map and
the base address of the other MC.
----------------------------------------------------------------------
Note that the PB (Compatibility PB in an 450GX dual PB system) is
responsible for claiming any unclaimed transactions on the host system
bus. Therefore, any memory space access that is above the top of
system main memory is claimed by the PB.
The MC has two registers located in the processor’s I/O space (0CF8h
and 0CFCh) that are used to configure the MC. See the Register
Description section for details.
3.2 Host Bus Interface
The Pentium Pro processor bus provides an efficient, reliable
interconnect between multiple Pentium Pro processors and the PB and
MC. The bus provides 36 bits of address, 64 bits of data, protection
signals needed to support data integrity, and the control signals to
maintain a coherent shared memory in the presence of multiple caches.
The Pentium Pro processor bus achieves high bus efficiency by
providing support for multiple, pipelined transactions and deferred
replies. A single Pentium Pro processor may have up to four
transactions outstanding at the same time, and can be configured to
support up to eight transactions active on the Pentium Pro processor
bus at any one time. The MC supports up to four transactions that
target its associated memory space. The MC contains read and write
buffers for memory accesses.
AERR#. An AERR# on the host bus stops traffic in the memory
controller. Reporting is done by the 82454 (PB).
BINIT#. A BINIT# on the Host bus resets the 450KX/GX host bus state
machines. This allows for logging or recovery from catastrophic bus
errors. Note that during the last clock of a BINIT# pulse, ADS# may
not be asserted as this will start the host bus state machine
prematurely.
3.3 DRAM Interface
In the following discussion the term row refers to the set of memory
devices that are simultaneously selected by a RAS# signal. A row may
be composed of two or more single-sided SIMMs, or one side (the same
side) from two or more double-sided SIMMs. An interleave is 72-bits
wide (64 data bits plus 8 bits of ECC) and requires two 36 bit
SIMMs. The term page refers to the data within a row that is selected
by a row address and is held active in the device waiting for a column
address to be asserted.
The MC interfaces the main memory DRAM to the host bus. For the 450KX,
two basic DRAM configurations are supported—2-way interleaved (or 2:1
interleaved), and non-interleaved (or 1:1 interleaved). In the 2-way
and non-interleaved configurations, a row is made up of 4 SIMM sides
and 2 SIMM sides respectively. There can be up to 1 Gbyte of DRAM for
a 2-way interleaved configuration and 512 Mbytes of DRAM for a
non-interleaved configuration as shown in Table 22. The MC is fully
configurable through the MC’s configuration registers.
----------------------------------------------------------------------
For the 450GX, three basic DRAM configurations are supported—4-way
interleaved (4:1 interleaved), 2-way interleaved, and
non-interleaved. In the 4-way interleaved configuration, a row is
made up of 8 36-bit SIMM sides. In the 2-way interleaved and
non-interleaved configurations, a row is made up of 4 SIMM sides and
2 SIMM sides respectively. There can be up to 4 Gbytes of DRAM for a
4-way interleaved configuration, 2Gbytes for a 2-way interleaved
configuration, and 1Gbyte for a non-interleaved configuration.
----------------------------------------------------------------------
Configurations cannot be mixed. The MC does not support portions of
the memory being 2-way interleaved and other portions being
non-interleaved. The system does, however, support a 2-way interleaved
design in which one interleave is populated (operates as a
non-interleaved configuration). There is no restriction on which
interleave is populated (0 or 1) to form a non-interleaved
configuration, as long as all rows are populated in the same way.
----------------------------------------------------------------------
The 450GX MC does not support portions of the memory being 4-way
interleaved and other portions being non-interleaved or 2-way
interleaved. The system does, however, support a 4-way or 2-way
interleaved design in which one interleave is populated (operates as
a non-interleaved configuration) or a 4-way interleaved design in
which two interleaves are populated (operates as a 2-way
configuration). There is no restriction on which interleaves are
populated to form a non-interleaved or 2-way interleaved
configuration, as long as all rows are populated in the same way.
----------------------------------------------------------------------
Table 22 [see datasheet] provides a summary of the characteristics of
memory configurations supported by the 450KX/GX MC. Minimum values
listed are obtained with single-sided SIMMs, and maximum values are
obtained with doublesided SIMMs.
***Configurations:...
***Features:...
**
**Support Chips:
**82091AA Advanced Interface Peripheral (AIP) c93...
**8289 Bus Arbiter (808x) c79...
**82289 Bus Arbiter for iAPX 286 Processor Family c83...
**82258 Advanced Direct Memory Access Coprocessor(ADMA) 01/01/84...
**82335 High-Integration Interface Device For 386SX c:Nov88...
**82360SL I/O Subsystem 10/05/90...
**82370 Integrated System Peripheral (for 82376) c:Oct88...
**82371FB/SB PCI ISA IDE Xcelerator 82371FB/82371SB (PIIX/3) 01/31/95...
**82371MX Mobile PCI I/O IDE Xcelerator (MPIIX) 11/01/95...
**82371AB PCI-TO-ISA / IDE Xcelerator 82371AB (PIIX4) 02/17/97...
**82374/82375 PCI-EISA Bridge (82374EB/82375EB, 374SB/375SB) c:Mar93...
**82378 System I/O (SIO) (82378IB and 82378ZB) c:Mar93...
**82379AB System I/O-APIC (SIO.A) <Dec94...
**82380 32-bit DMA Controller w/ Integrated Peripherals 02/01/87...
**82380FB/AB PCIset: 82380FB Mobile PCI-to-PCI Bridge(MPCI2) 02/17/97...
**82384 Clock Generator and Reset Interface c86...
**82385 32-bit Cache Controller for 80386 09/29/87...
**82385SX 32-bit Cache Controller for 80386SX 01/25/89...
**82395DX High Performance Smart Cache 06/18/90...
**82395SX Smart Cache 12/17/90...
**82396SX Smart Cache 12/17/90...
**82485 Turbo Cache (and 485Turbocache) c90...
**82489DX Advanced Programmable Interrupt Controller 10/12/92...
**82495DX/490DX DX CPU-Cache Chip Set <Sep91...
**82495XP/490XP Cache Controller / Cache RAM (for i860) 06/05/91...
**82496/491 Cache Controller / Cache RAM (for P5 Pentium) 03/22/93...
**82497/492 Cache Controller / Cache RAM (for P54 Pentium) <Nov94...
**82498/493 Cache Controller / Cache RAM (for P54 Pentium) <Nov94...
**
**Later chipsets (basic spec):
**440 series:...
**450NX (?) 06/29/98:...
**????? (Profusion) c:99
Chips:
Memory Access Controller (MAC)
Data Interface Buffer (DIB)
CPUs: 8x P-III Xeon Oct
DRAM Types: SDRAM PC100 2-way Interleave dual channel
Max Mem: 32GB
ECC/Parity: ECC
AGP speed: N/A
Bus Speed: 100
PCI Clock/Bus: 1/3 PCI-66/64
**800 series...
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