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**M1207 286 Single Chip [no datasheet] ?...
**M1217/M1209 386SX/SLC Single Chip (40MHz) [no datasheet] c91...
**M1219 386DX/486 ISA Cache? Single Chip [no datasheet] ?
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**M1439/31/45 486 VLB/PCI/ISA [no datasheet, some info] <May95...
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**82450KX/GX PCIset (Pentium Pro) KX/GX (Mars/Orion) 11/01/95
***Notes:...
***Info:
****General:...
****82454KX/GX PCI Bridge (PB):
The 82454KX/GX PB are single-chip PC-compatible host-to-PCI bridges. A
rich set of Host-to-PCI and PCI-to-Host bus transaction translations
optimize bus bandwidth and improve system performance. All ISA and
EISA regions are supported. Three programmable memory gaps can be
created—a PCI Frame Buffer Region and two general-purpose memory gaps
(the Memory Gap Region and the High Memory Gap Region). The PB has a
synchronous interface to the Pentium Pro processor bus and supports a
derived clock for the synchronous PCI interface. The PB generates and
checks ECC over the host data bus (82545GX only), and generates and
checks parity over the address and request/response signal lines (both
82454KX and 82454GX). The PB also checks address and data parity on
the PCI bus. For the 82454GX, two PBs can be used in a system.
The Intel 450KX/GX PCIsets may contain design defects or errors known
as errata. Current characterized errata are available upon request.
3.0 PB FUNCTIONAL DESCRIPTION
This section describes the PB functions and hardware interfaces
including the I/O and Memory Map, Host bus, PCI bus, and Dual-bridge
Architectures. Data Integrity and Error Handling are covered. Clock,
Reset, and PB configuration are also covered.
3.1 Memory and I/O Map
The 82454KX/GX PB provides the interface between the host bus and the
PCI bus. Memory transactions can be sent from the PCI bus to the host
bus and from the host bus to the PCI bus. Gaps and positive decode
ranges can be programmed via the configuration registers. For the
82454KX, I/O transactions can be sent from the host bus to the PCI
bus. However, I/O transactions can not be sent from the PCI bus to the
host bus.
----------------------------------------------------------------------
For the 82454GX, both memory and I/O transactions can be sent from
the PCI bus to the host bus and from the host bus to the PCI
bus. Memory and I/O gaps and positive decode ranges can be
programmed via the configuration registers.
----------------------------------------------------------------------
If an access is enabled to be forwarded from the host bus to the PCI
bus, the corresponding access on the PCI bus is ignored (not forwarded
to the host bus). Conversely, if an access is enabled to be forwarded
from the PCI bus to the host bus, the corresponding access on the host
bus is ignored (not forwarded to the PCI bus).
The PB and MC perform a positive address decode of each host
transaction and one default device handles the unclaimed
transactions. In a standard PC system, unclaimed transactions are sent
to the ISA bus. Thus, the PB (Compatibility PB in an 82454GX dual PB
system) is the default responder on the host bus.
3.1.1 MEMORY ADDRESS MAP [see datasheet]
3.1.2 I/O ADDRESS MAP [see datasheet]
3.2 Host Bus Interface
The Pentium Pro processor bus provides an efficient, reliable
interconnect between multiple Pentium Pro processors and the PB and
MC. The bus provides 36 bits of address, 64 bits of data, protection
signals needed to support data integrity, and the control signals to
maintain a coherent shared memory in the presence of multiple caches.
The Pentium Pro processor bus achieves high bus efficiency by
providing support for multiple, pipelined transactions and deferred
replies. A single Pentium Pro processor may have up to four
transactions outstanding at the same time, and can be configured to
support a total of either one or eight transactions active on the
Pentium Pro processor bus at any one time. The PB supports up to eight
active transactions on the host bus (In-Order Queue depth of
8). During the host bus reset and configuration, all host bus devices
are configured to support either one or eight transactions in their
In-Order Queue.
The number of transactions that can target a particular bus client is
configured separately from the total number of transactions allowed on
the bus. The PB accepts up to four transactions into the Outbound
Request Queue that target its associated PCI bus.
The PB provides four 32-byte buffers for outbound data (host-to-PCI
writes or PCI reads from the host bus), and four 32-byte buffers for
inbound data (PCI-to-host writes or CPU reads from PCI).
As a host bus master, the PB does not support deferred responses. The
EXF1# extended function signal (Defer Enable) will never be asserted
for a host transaction initiated by the PB.
The host bus supports ECC over the data bus, and parity protection
over the address, request, and response lines. The PB generates and
checks ECC over the data lines (82454GX only), and generates and
checks parity over the address and request/response signal lines (both
82454KX/GX). Note, ECC generation and checking on the data lines and
parity generation and checking on the request/response lines can be
enabled or disabled during system configuration.
3.3 PCI Bus Interface
The PB has a standard master/slave PCI bus interface. All legal PCI
(PCI specification 2.0) bus transactions are supported. PCI cycle
termination and error logging/reporting are discussed in the Data
Integrity and Error Handling section. The PCI arbitration unit is not
implemented in the PB.
PCI Locks. Systems which support PCI initiate locks (either inbound
locks or peer-to-peer) must configure the arbiter for full bus locks
rather than resource locks. The PB will not recognize resource locks
made by peer-to-peer accesses. When a PCI master asserts LOCK# while
targeting the PB, the locked PCI transactions are converted to locked
host bus transactions. The host bus lock continues as long as the PCI
master asserts LOCK# for exclusive access to the PB. The host bus lock
is assisted by the bridge continuing to assert BPRI# as long as the
PCI bus is asserting resource lock to the bridge. Additional locked
CPU transactions are issued if the PCI master continues to burst.
In systems in which target abort reporting is disabled, the write
portion of a lock will be committed even when the read portion is
aborted.
Host Bus Locks. Any transactions that target the bridge during a host
bus lock are converted into a similar PCI lock transaction. The lock
on the PCI bus is held until the host bus lock is released. Locks
over the Frame Buffer region can be disabled through a mode bit in the
PCI Frame Buffer Range Register.
Indivisible Operations. CPU initiated read operations that cross a
Dword boundary (e.g., Read 8 Bytes, Read 16 Bytes, etc.) are
indivisible operations on the host bus. However, since the PCI
protocol allows a target device to disconnect at any point in a
transfer sequence, these operations must be locked indivisible on the
PCI bus. The PB optionally locks all CPU initiated reads that cross a
Dword boundary. This mode is enabled by setting the Lock Atomic Reads
in the PB Configuration Register. CPU initiated Write operations
(e.g., Write 8 Bytes, Write 16 Bytes, etc.) are indivisible operations
on the host bus. However, these accesses can not be made indivisible
on the PCI bus because the PCI Specification states that the first
transaction of a locked operation must be a read. Therefore, software
must not rely upon the atomicity of CPU initiated write transactions
greater then 32 bits once they are translated to the PCI bus.
Software Generated Special Cycles. This optional feature is not
supported by the 450KX/GX PCIset.
3.4 Data Integrity and Error Handling
Several data integrity features are included in the PB. These include
ECC on the host data bus (450GX only), parity on the host address,
parity on the CPU Request/Response signals, and parity on the PCI
bus. Error logging (setting a status bit) and reporting (generating an
error signal) are controlled by the PCICMD Register (04–05h), PCISTS
Register (06–07h), ERRCMD Register (70h), ERRSTS Register (71h),
EXERRCMD Register (C0–C3h), and EXERRSTS Register (C4–C7h).
3.4.1 HOST BUS ERRORS [see datasheet]
3.4.2 PCI BUS ERRORS [see datasheet]
3.5 Dual PB Architectures (82454GX Only)
----------------------------------------------------------------------
In a dual bridge system, one PB is configured as the default bridge
(Compatibility PB) after power-on RESET. The Compatibility PB
provides a path to the ISA bus devices needed in a PC-compatible
system such as the boot ROM. The Compatibility PB is the highest
priority bridge in a dual bridge system to ensure a fast enough
response time for ISA bus masters. See the Clocks, Reset, and
Configuration section for details on configuring a PB as the
Compatibility PB.
Multiple I/O APICs
In a dual PB system, the auxiliary PCI bus interrupt requests are
routed to the auxiliary bus I/O APIC. When booting the system with
one processor, the IRQ control logic is enabled, feeding the
interrupt request to the standard interrupt controller in the
ESC. When the system is in multiprocessor mode, the routing logic is
disabled after ensuring PB buffer coherency, and interrupt requests
are forwarded to the processors via the APIC bus. The Intel 82379AB
(SIO.A) may be utilized as a stand-alone I/O APIC device. However,
the additional logic for interrupt/memory consistency and the
interrupt steering logic is not provided in the SIO.A and must be
implemented externally.
Dual Bridge Arbitration for the Host Address Bus
The PB requests the host address bus with BPRI#. However, only one
bridge is allowed to drive BPRI# at a time. With two PBs, an
internal arbiter is used to establish bus ownership. This
arbitration is transparent to the CPU and other symmetric bus
agents.
In a two PB system, the compatibility PB acts as the arbitration
unit between it and the other PB, as shown in Figure 6 [see
datasheet]. When a PB is programmed to be the arbitration unit, its
IOGNT# is the input for the IOREQ# from the other bridge and IOREQ#
is the output to IOGNT# of the other bridge.
Figure 7 [see datasheet] shows the minimum arbitration timing in a
two bridge system. IOGNT# may assert later than shown and IOREQ# may
negate later than the two clocks after IOGNT# negates.
The arbiter bridge can assert BPRI# as long as it has not asserted
its IOREQ# (Grant to the other bridge) and BPRI# is not currently
driven. In turn, the other bridge, after receiving it’s IOGNT#,
samples BPRI# released before assuming ownership of BPRI#. This
allows the BPRI# arbitration to be performed in parallel with
another bridge transfer. This timing is shown in Figure 8. [see
datasheet]
Bridge-to-bridge misaligned (split) locks are not recommended and
could cause deadlock in systems.
Bridge-to-Bridge Communication
PB-to-PB communication is supported by the PB, but is not recom-
mended for optimal performance.
PB-to-PB transactions involving a standard bus bridge (SIO,
PCEB/ESC) require special precautions to avoid deadlock and latency
problems. The PB does NOT support PB-to-PB transactions from agents
that cannot be backed off such as those originating on an ISA or
EISA bus and targeting a device on a different PB’s PCI bus. Any
device that asserts FLSHBUF# must be targeting a device on the local
PCI bus or the host bus.
Dual PB Configuration (82454GX only)
During a power-on reset (PWRGD asserted), IOREQ# and IOGNT# provide
a unique identification number for each PB (PBID). The PBID is part
of the PB’s PCI Bridge Device Number and is available to programmers
via the BDNUM Register (offset 49h). The Dual PB system must have a
pull-up and a pull-down as shown in Figure 9. The encoding for these
signals is shown in Table 10. [see datasheet]
----------------------------------------------------------------------
3.6 Peripheral Operation and Performance
The 82454 PB is designed for optimum processor performance to get the
most out of a Pentium Pro processor’s capabilities. In systems with
multiple PCI devices, one must take into account the architecture of
the 82454 PB in order to maximize overall system performance.
3.6.1 MATCHING PERIPHERALS TO THE 450KX/GX [see datasheet]
3.6.2 DISTRIBUTING PERIPHERALS WITHIN THE I/O SUBSYSTEM
While this is not necessary for system operation, systems implementing
dual 82454 PBs have additional latitude to isolate high speed I/O
devices from competing system traffic initiated by the CPU.
All graphics and the vast majority of I/O space communication (such as
keyboard controller, system timer, and interrupt support) will be
directed to the primary PCI bus behind the Compatibility 82454
PB. (This is the bus with a subsequent connection via another bridge
to an ISA or EISA bus.) This processor traffic will compete with bus
mastering peripheral devices attempting to move data to and from
system memory. It is desirable then to place latency sensitive devices
behind the Auxiliary 82454 PB, to isolate them from competing CPU
traffic.
In a full system configuration, in which all PCI slots are occupied,
it is preferable to segregate peripherals intelligently. Limit the
primary PCI bus to graphics accelerators and SCSI RAID controllers,
leaving Auxiliary 82454 PB PCI slots free for latency-sensitive
devices such as network adapters. In systems connecting a large number
of network adapters, divide them evenly between the two busses to
minimize the amount of latency-sensitive competition at any one point
in the system.
3.6.3 PCI-TO-PCI BRIDGES [see datasheet]
3.6.4 BIOS PERFORMANCE TUNING [see datasheet]
3.7 Clock, Reset, and Configuration
3.7.1 SYSTEM CLOCKING [see datasheet]
3.7.2 SYSTEM RESET [see datasheet]
3.7.3 SYSTEM INITIALIZATION [see datasheet]
3.7.5 USING THE 82379AB SIO.A PCI-TO-ISA BRIDGE WITH THE 450KX/GX
There is an anomaly with systems that use the 82379AB (SIO.A) during
targeted PCI Resets. In addition, 450GX/KX systems can boot improperly
at power-up and react improperly to the assertion of the Pentium Pro
bus signal BINIT# signal (due to the assertion of PCIRST# via BINIT#).
The SIO.A drives SMI#, ALT_A20, INT, NMI, IGNNE#, ALT_RST#, and
STPCLK# low while PCIRST# is asserted low, and does not drive them
high until after PCI reset is released. An anomaly can exist with
these seven signals remaining low during and immediately after PCIRST#
is negated. The three instances in which this can cause an anomaly
are: during a targeted PCI Reset, and in a 450GX/KX-Pentium Pro
processor system, both during power-up and when BINIT# is asserted on
the Pentium Pro processor bus.
....[see datasheet]
3.8 Host to PCI Bus Command Translation [see datasheet]
3.9 PCI to Host Bus Command Translation [see datasheet]
****Memory Controller (MC) 82453KX/GX (DC), 82452KX/GX (DP), 82451KX/GX (MIC)...
***Configurations:...
***Features:...
**
**Support Chips:
**82091AA Advanced Interface Peripheral (AIP) c93...
**8289 Bus Arbiter (808x) c79...
**82289 Bus Arbiter for iAPX 286 Processor Family c83...
**82258 Advanced Direct Memory Access Coprocessor(ADMA) 01/01/84...
**82335 High-Integration Interface Device For 386SX c:Nov88...
**82360SL I/O Subsystem 10/05/90...
**82370 Integrated System Peripheral (for 82376) c:Oct88...
**82371FB/SB PCI ISA IDE Xcelerator 82371FB/82371SB (PIIX/3) 01/31/95...
**82371MX Mobile PCI I/O IDE Xcelerator (MPIIX) 11/01/95...
**82371AB PCI-TO-ISA / IDE Xcelerator 82371AB (PIIX4) 02/17/97...
**82374/82375 PCI-EISA Bridge (82374EB/82375EB, 374SB/375SB) c:Mar93...
**82378 System I/O (SIO) (82378IB and 82378ZB) c:Mar93...
**82379AB System I/O-APIC (SIO.A) <Dec94...
**82380 32-bit DMA Controller w/ Integrated Peripherals 02/01/87...
**82380FB/AB PCIset: 82380FB Mobile PCI-to-PCI Bridge(MPCI2) 02/17/97...
**82384 Clock Generator and Reset Interface c86...
**82385 32-bit Cache Controller for 80386 09/29/87...
**82385SX 32-bit Cache Controller for 80386SX 01/25/89...
**82395DX High Performance Smart Cache 06/18/90...
**82395SX Smart Cache 12/17/90...
**82396SX Smart Cache 12/17/90...
**82485 Turbo Cache (and 485Turbocache) c90...
**82489DX Advanced Programmable Interrupt Controller 10/12/92...
**82495DX/490DX DX CPU-Cache Chip Set <Sep91...
**82495XP/490XP Cache Controller / Cache RAM (for i860) 06/05/91...
**82496/491 Cache Controller / Cache RAM (for P5 Pentium) 03/22/93...
**82497/492 Cache Controller / Cache RAM (for P54 Pentium) <Nov94...
**82498/493 Cache Controller / Cache RAM (for P54 Pentium) <Nov94...
**
**Later chipsets (basic spec):
**440 series:...
**450NX (?) 06/29/98:...
**????? (Profusion) c:99
Chips:
Memory Access Controller (MAC)
Data Interface Buffer (DIB)
CPUs: 8x P-III Xeon Oct
DRAM Types: SDRAM PC100 2-way Interleave dual channel
Max Mem: 32GB
ECC/Parity: ECC
AGP speed: N/A
Bus Speed: 100
PCI Clock/Bus: 1/3 PCI-66/64
**800 series...
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