[Home] [This version is outdated, a new version is here]
*Title...
*Search:...
*Read Me/FAQ/General Info...
**A note on VESA support of 486 chipsets.
Many chipsets state  that they support VESA local  bus.  In some cases
these actually  implement VLB somewhat  like PCI, where it  is entirly
decoupled from the CPU bus. Chipsets  that do not state they work with
VLB,  may  be found  on  motherboards  that  contain VLB  slots.   VLB
is  *basically*  The 486  CPU  pinout in  a  slot  form. Unless  these
m/boards contain  some additional  chips, there VLB  implementation is
directly coupled to the CPU.

**Datasheets:...
*_IBM...
*ACC Micro...
*ALD...
*ALi...
*AMD . . . . . . . [no datasheets, some info]...
*Chips & Technologies...
*Contaq  . . . . . [no datasheets, some info]...
*Efar Microsystems [no datasheets, some info]...
*ETEQ...
*Faraday...
*Forex . . . . . . [List only, no datasheets found]...
*Intel...
**82430FX     PCIset (Pentium) FX (Triton I) (82437FX/82438FX)01/31/95
***Notes:...
***Info:...
***Configurations:...
***Features:
o   Supports all 3V Pentium Processors
o   Integrated Second Level Cache Controller
    - Direct Mapped Organization
    - Write-Back Cache Policy
    - Cacheless, 256-Kbyte, and 512-Kbyte
    - Standard Burst and Pipelined Burst SRAMs
    - Cache Hit Read/Write Cycle Timings at 3-1-1-1 with Burst or 
      Pipelined
      Burst SRAMs
    - Back-to-Back Read Cycles at 3-1-1-1-1-1-1-1 with Burst or 
      Pipelined Burst SRAMs
    - Integrated Tag/Valid Status Bits for Cost Savings and Performance
    - Supports 5V SRAMs for Tag Address
o   Integrated DRAM Controller
    - 64-Bit Data Path to Memory
    - 4 Mbytes to 128 Mbytes Main Memory
    - EDO/Hyper Page Mode DRAM (x-2-2-2 Reads) or Standard Page Mode 
      DRAMs
    - 5 RAS Lines
    - 4 Qword Deep Buffer for 3-1-1-1 Posted Write Cycles
    - Symmetrical and Asymmetrical DRAMs
    - 3V or 5V DRAMs
o   EDO DRAM Support
    - Highest Performance with Burst or Pipelined Burst SRAMs
    - Superior Cacheless Designs
o   Fully Synchronous 25/30/33 MHz PCI Bus interface
    - 100 MB/s instant Access Enables Native Signal Processing (NSP) on
      Pentium Processors
    - Synchronized CPU-to-PCI Interface for High Performance Graphics
    - PCI Bus Arbiter: PIIX and Four PCI Bus Masters Supported
    - CPU-to-PCI Memory Write Posting with 4 Dword Deep Buffers
    - Converts Back-to-Back Sequential CPU to PCI Memory Writes to PCI
      Burst Writes
    - PCI-to-DRAM Posting of 12 Dwords
    - PCI-to-DRAM up to 120 Mbytes/Sec Bandwidth Utilizing Snoop Ahead
      Feature
o   NAND Tree for Board-Level ATE Testing
o   208 Pin OFP for the 82437FX System Controller (TSC); 100 Pin-QFP 
    for Each 82438FX Data Path (TDP)
o   Supported Kits
    - 82437FX ISA Kit (TSC, TDPs, PIIX)

**82430MX     PCIset (Pentium) MX (Mobile Triton)(82437/438MX)11/01/95...
**82430HX     PCIset (Pentium) HX (Triton II) (82439HX)       02/12/96...
**82430VX     PCIset (Pentium) VX (Triton II) (82437VX/82438) 02/12/96...
**82430TX     PCIset (Pentium) TX (Triton II) (82439TX)       02/17/97...
**82450KX/GX  PCIset (Pentium Pro) KX/GX (Mars/Orion)         11/01/95...
**
**Support Chips:
**82091AA     Advanced Interface Peripheral (AIP)                  c93...
**8289        Bus Arbiter (808x)                                   c79...
**82289       Bus Arbiter for iAPX 286 Processor Family            c83...
**82258       Advanced Direct Memory Access Coprocessor(ADMA) 01/01/84...
**82335       High-Integration Interface Device For 386SX      c:Nov88...
**82360SL     I/O Subsystem                                   10/05/90...
**82370       Integrated System Peripheral (for 82376)         c:Oct88...
**82371FB/SB  PCI ISA IDE Xcelerator 82371FB/82371SB (PIIX/3) 01/31/95...
**82371MX     Mobile PCI I/O IDE Xcelerator (MPIIX)           11/01/95...
**82371AB     PCI-TO-ISA / IDE Xcelerator 82371AB (PIIX4)     02/17/97...
**82374/82375 PCI-EISA Bridge (82374EB/82375EB, 374SB/375SB)   c:Mar93...
**82378       System I/O (SIO) (82378IB and 82378ZB)           c:Mar93...
**82379AB     System I/O-APIC (SIO.A)                           <Dec94...
**82380       32-bit DMA Controller w/ Integrated Peripherals 02/01/87...
**82380FB/AB  PCIset: 82380FB Mobile PCI-to-PCI Bridge(MPCI2) 02/17/97...
**82384       Clock Generator and Reset Interface                  c86...
**82385       32-bit Cache Controller for 80386               09/29/87...
**82385SX     32-bit Cache Controller for 80386SX             01/25/89...
**82395DX     High Performance Smart Cache                    06/18/90...
**82395SX     Smart Cache                                     12/17/90...
**82396SX     Smart Cache                                     12/17/90...
**82485       Turbo Cache (and 485Turbocache)                      c90...
**82489DX       Advanced Programmable Interrupt Controller    10/12/92
***Notes:...
***Info:...
***Versions:...
***Features:...
**82495DX/490DX DX CPU-Cache Chip Set                           <Sep91...
**82495XP/490XP Cache Controller / Cache RAM (for i860)       06/05/91...
**82496/491     Cache Controller / Cache RAM (for P5 Pentium) 03/22/93...
**82497/492   Cache Controller / Cache RAM (for P54 Pentium)    <Nov94...
**82498/493   Cache Controller / Cache RAM (for P54 Pentium)    <Nov94...
**
**Later chipsets (basic spec):
**440 series:...
**450NX  (?)            06/29/98:...
**?????  (Profusion)    c:99...
**800 series...
*Headland/G2...
*HMC (Hulon Microelectronics)...
*Logicstar...
*Motorola...
*OPTi...
*PC CHIPS/Amptron/Atrend/ECS/Elpina/etc...
*SIS...
*Symphony...
*TI (Texas Instruments)...
*UMC...
*Unresearched:...
*VIA...
*VLSI...
*Western Digital...
*Winbond...
*ZyMOS...
*General Sources:...