[Home] [This version is outdated, a new version is here]
*Title...
*Search:...
*Read Me/FAQ/General Info...
*_IBM...
*ACC Micro...
*ALD...
*ALi...
*AMD . . . . . . . [no datasheets, some info]...
*Chips & Technologies...
*Contaq . . . . . [no datasheets, some info]...
*Efar Microsystems [no datasheets, some info]...
*ETEQ...
*Faraday...
*Forex . . . . . . [List only, no datasheets found]...
*Intel...
**82350DT EISA Chip Set 04/22/91
***Notes:...
***Info:
****General:...
****82351 Local I/O EISA Support Peripheral (LIO.E)...
****82352DT EISA Bus Buffer (EBB)...
****82353 Advanced Data Path Device...
****82357 Integrated System Peripheral (ISP)...
****82358DT EISA Bus Controller...
****82359 DRAM Controller
The 82359 DRAM Controller is a highly integrated advanced memory
controller capable oi supporting today’s Intel386 and Intel486 high
performance microprocessors. Its decoupled handshake protocol gives
the 82359 independence over processor type and speed, allowing the
system designer to implement a variety of CPU/ cache combinations.
The 82359 implements a dual ported architecture by providing two
independent address paths to main memory. This allows activity on each
bus to run independently of the other, giving each greater bus
throughput and decreased bus latency.
The 82359 provides address control, refresh generation. critical DRAM
timing generation and by working closely with two 82353 Advanced Data
Path devices, provides a highly integrated 32-bit dual ported memory
controller in just three VLSI components.
1.0 INTRODUCTION
The 82359 DRAM Controller is a highly integrated EISA DRAM memory
controller based on a dual ported memory architecture. It provides
address and control signals for DRAM based main memory and it works
very closely with two 82353 Advanced Data Path devices.
The 82359 may operate in one of two modes: (1) Standard Mode in which
the 82359 connects directly to the EISA address bus; and (2) Buffered
Mode, in which a new bus exists between the 82359 and the EISA bus and
functions similar to the host bus. In this mode, the EISA bus is
"buffered" from the 82359. For a full discussion of Buffered and
Standard Mode, see the "82350DT System Architecture Overview"
document.
The 82359 has two ports, or address gateways, to main memory; one
exclusively for the host and one exclusively for EISA. This allows CPU
activity to be isolated from EISA bus activity, allowing the host to
run out of main memory at the same time system bus (EISA) activity is
occurring. This dual ported architecture provides four routes which a
cycle may follow: (1) Host to main memory; (2) Host to system slave;
(3) System master to main memory and; (4) System address to host cache
(for cache line invalidation).
One port, labeled “Host Port", provides a one-way path for host cycles
to DRAM memory or to the system bus. it is capable of accepting a
32-bit host address and host cycle definition. From the address and
cycle definition, the 82359 determines if the cycle is bound for main
memory, in which case the 82359 executes a DRAM cycle, or if not to
main memory, the 82359 forwards the cycle to the system bus. Although
the host port is considered one-way in direction in that it is only
capable of receiving host originated cycles, it does drive the host
address lines when forwarding cache invalidation addresses to the host
cache (if one exists).
The second port, labeled "System Port", acts as the gateway to/ from
the system bus. Unlike the host port, the system port is
bi-directional, capable of sending as well as receiving 32-bit
addresses and system bus cycle definitions. The system port accepts
system bus cycles and, if the cycle is to an address contained in main
memory, it executes the DRAM cycle. If the address of the system cycle
is not contained in main memory, no action is taken by the 82359.
Since the 82359 was designed to support an EISA based expansion bus,
it closely communicates with the 82358DT EISA Bus Controller
(EBC). All host-to-system cycles are sent through the 82359 to the EBC
for correct EISA/ ISA cycle generation. All EISA bus activity is
directly monitored and interpreted by the 82359, and the 82359
automatically acts upon EISA cycles to main memory without EISA
protocol translation by the EBC.
The 82359 does not follow the typical ADS# and READY# protocol of the
microprocessor. Instead, it uses a clockless protocol on both the host
and system ports which isolates the CPU clock from the DRAM
controller. This allows the 82359 to become CPU frequency
independent.
A typical design would take the cycle definition (M/IO#, W/R#, D/C#)
and ADS# of the CPU and interpret these to communicate with the 82359,
telling it to start a cycle and what type of cycle is required. The
82359 decodes the address presented with the start of the cycle and
returns a 3-bit code for the cycle length. From this cycle length, the
protocol converter knows when to return READY# to the CPU.
The 82359 contains many programmable registers which control functions
such as memory block enable/remap/shadow, DRAM timing generation,
memory array population, and memory cycle length to name a few. These
registers are typically programmed by the BIOS at power-up. It is
through these registers that the 82359 achieves its flexibility.
Four registers are provided for memory array population
information. The BIOS typically tests memory at power-up and provides
DRAM SIMM size and population information to the 82359.
DRAM access times of 60, 70, or 80 ns are supported by the 82359. To
facilitate the critical timings specific to each speed of the DRAM,
the 82359 has programmable registers which access an internal delay
line. Through these programmable timing registers, DRAM parameters
such as RAS# precharge, RAS# to CAS# delay, etc. can be tailored to
the DRAM’s required times with 2.61 ns resolution.
Portions of the memory array may be individually disabled, remapped,
write-only or read-only under programmable register control. Through
the use of these registers, BIOS may be shadowed to DRAM. Also the
memory map may be configured to "jump over" areas which Contain other
system functions (such as video, BIOS, etc.) by disabling portions of
DRAM in 16k increments. Memory in the 512k-1M range may be disabled
and remapped to the top of main memory in 64k blocks.
The 82359 provides four Programmable Attribute Map (PAM) registers to
be used in systems which utilize caches on the host bus. Three bits of
attribute are provided for each range: (1) Cache Enable, (2) Write
Protect, and (3) a User-Defined bit. These registers allow software to
determine the attributes for a programmable range size at a prog-
rammable starting address.
Eight LIM registers are provided for those systems which take
advantage of the Lotus/lntel/Microsoft convention for expanded
memory. These registers may be programmed to swap 16k pages of memory
from anywhere in the lower 16M address range into and out of DOS
accessibility.
The 82359 is designed to support write-through caches on the host
bus. System write cycles are sent to the host cache as snoop
cycles. Also, the 82359 performs "Snoop Filtering" which eliminates
needless snoop cycles. Should a system write cycle occur to a location
contained in the cache line which the 82359 invalidated by the
previous snoop cycle, the 82359 will not broadcast the second,
redundant snoop to the host. By eliminating redundant snoops, the host
bus has increased bandwidth.
As EISA masters become more and more abundant, main memory
accessibility becomes an increasingly important factor. With many EISA
master devices installed in a system, the portion of memory bandwidth
available to the CPU decreases significantly. To eliminate inefficient
allocation of memory bandwidth, the 82359 has internal throttles which
can be programmed to hold off memory ownership requests for a deter-
mined period of time so that others who desperately require memory
bandwidth can have a greater time-slice than EISA arbitration
allows. The net effect of these throttles allows the main memory
ownership resource to be allocated for best system performance.
The 82359 provides two modes of DRAM refresh generation: (1) Coupled
Refresh, in which the refresh timing is provided by the EISA bus, and
(2) Decoupled Refresh, in which the 82359 refreshes main memory by
generating the refresh request and address internally.
To facilitate the CPU frequency independence of the 82359, a new host
bus protocol was devised. This protocol does not follow the
synchronous ADS# and RDY# of the processor. Instead, it is async-
hronous in nature in that it has no clock. This protocol is
implemented by an external Programmable State Tracker (or PST) which
converts the CPU’s ADS# and FtDY# protocol to the asynchronous
protocol used by the 82359. This PST can typically be implemented in
a two or three PLD solution.
Although the protocol is asynchronous, it does not detriment CPU to
memory performance like other asynchronous protocols. This is
achieved by the unique implementation of the protocol. The protocol
defines two types of cycles; (1) the Deterministic Cycle, and; (2) the
Non-deterministic Cycle. Deterministic cycles are cycles to main
memory. The exact length of these cycles is known by the 82359 at the
beginning of the cycle since it is aware of exactly how long that
cycle to memory (page hit, page miss) will require for completion. The
82359 immediately relays that information to the host PST via a "DRAM
Page Hit" indicator and a 3-bit code containing wait state
information. From this, the host PST knows exactly when to send the
RDY# to the CPU. Thus the RDY# is returned at the exact moment the
memory cycle finishes and no synchronization penalty is incurred.
Non-deterministic cycles are host cycles to system bus slaves or
locked cycles. Before these cycles can complete, the host must gain
ownership of the system bus and thus, arbitration may be
required. Since the 82359 does not know exactly how long the host must
wait before gaining system bus ownership, or exactly how long the
host-to-system cycle will require to complete (due various speeds of
system slaves), the 82359 can not return an exact cycle length to the
host CPU. Instead, an asynchronous signal is used to indicate the
completion of the host-to-system cycle. In this case, a one CPU clock
synchronization penalty is paid when returning RDY#. It is important
to note that host-to-system cycles are the only cycles which pay this
synchronization penalty and that the more important host-to-main
memory cycles pay no synchronization penalty whatsoever.
****82355 Bus Master Interface Controller (BMIC)...
***Configurations:...
***Features:...
**82420TX/ZX PCIset (for 486) TX (Saturn), ZX (Saturn II) c:Nov92...
**82420EX PCIset (for 486) EX (Aries) (82425EX/82426EX) <Dec94...
**82430LX PCIset (Pentium) LX (Mercury) (82433LX/82434LX) 03/22/93...
**82430NX PCIset (Pentium) NX (Neptune) (82433NX/82434NX) Mar94...
**82430FX PCIset (Pentium) FX (Triton I) (82437FX/82438FX)01/31/95...
**82430MX PCIset (Pentium) MX (Mobile Triton)(82437/438MX)11/01/95...
**82430HX PCIset (Pentium) HX (Triton II) (82439HX) 02/12/96...
**82430VX PCIset (Pentium) VX (Triton II) (82437VX/82438) 02/12/96...
**82430TX PCIset (Pentium) TX (Triton II) (82439TX) 02/17/97...
**82450KX/GX PCIset (Pentium Pro) KX/GX (Mars/Orion) 11/01/95...
**
**Support Chips:
**82091AA Advanced Interface Peripheral (AIP) c93...
**8289 Bus Arbiter (808x) c79...
**82289 Bus Arbiter for iAPX 286 Processor Family c83...
**82258 Advanced Direct Memory Access Coprocessor(ADMA) 01/01/84...
**82335 High-Integration Interface Device For 386SX c:Nov88...
**82360SL I/O Subsystem 10/05/90...
**82370 Integrated System Peripheral (for 82376) c:Oct88...
**82371FB/SB PCI ISA IDE Xcelerator 82371FB/82371SB (PIIX/3) 01/31/95...
**82371MX Mobile PCI I/O IDE Xcelerator (MPIIX) 11/01/95...
**82371AB PCI-TO-ISA / IDE Xcelerator 82371AB (PIIX4) 02/17/97...
**82374/82375 PCI-EISA Bridge (82374EB/82375EB, 374SB/375SB) c:Mar93...
**82378 System I/O (SIO) (82378IB and 82378ZB) c:Mar93...
**82379AB System I/O-APIC (SIO.A) <Dec94...
**82380 32-bit DMA Controller w/ Integrated Peripherals 02/01/87...
**82380FB/AB PCIset: 82380FB Mobile PCI-to-PCI Bridge(MPCI2) 02/17/97...
**82384 Clock Generator and Reset Interface c86...
**82385 32-bit Cache Controller for 80386 09/29/87...
**82385SX 32-bit Cache Controller for 80386SX 01/25/89...
**82395DX High Performance Smart Cache 06/18/90...
**82395SX Smart Cache 12/17/90...
**82396SX Smart Cache 12/17/90...
**82485 Turbo Cache (and 485Turbocache) c90...
**82489DX Advanced Programmable Interrupt Controller 10/12/92...
**82495DX/490DX DX CPU-Cache Chip Set <Sep91...
**82495XP/490XP Cache Controller / Cache RAM (for i860) 06/05/91
***Notes:...
***Info:...
***Features:...
**82496/491 Cache Controller / Cache RAM (for P5 Pentium) 03/22/93...
**82497/492 Cache Controller / Cache RAM (for P54 Pentium) <Nov94...
**82498/493 Cache Controller / Cache RAM (for P54 Pentium) <Nov94...
**
**Later chipsets (basic spec):
**440 series:...
**450NX (?) 06/29/98:...
**????? (Profusion) c:99...
**800 series...
*Headland/G2...
*HMC (Hulon Microelectronics)...
*Logicstar...
*Motorola...
*OPTi...
**82C802 SCWB2 PC/AT Single Chip [no datasheet] ?
***Notes:...
**82C802G/GP System/Power Management Controller (cached) c:93...
**82C895 System/Power Management Controller (cached) c:Sep94...
**82C898 System/Power Management Controller (non-cache)c:Nov94...
**
**Support Chips:
**82C601/2 Buffer Devices <Nov94...
**82C822 PCIB (VLB-to-PCI bridge) c:94...
**Other:...
*PC CHIPS/Amptron/Atrend/ECS/Elpina/etc...
*SIS...
*Symphony...
*TI (Texas Instruments)...
*UMC...
*Unresearched:...
*VIA...
*VLSI...
*Western Digital...
*Winbond...
*ZyMOS...
*General Sources:...
(c) Copyright mR_Slugs Warehouse - All rights Reserved