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**82340DX Chip Set (VLSI) (82346/82345/82355) 01/08/90
***Notes:...
***Info:...
***Configurations:...
***Features:
o Three Chip ISA (Industry Standard Architecture) Chip Set Capable
of Use in 386 DX-Based Systems Up to 33 MHz
- 82346 System Controller
- 82344 ISA Bus Controller
- 82345 Data Buffer
o Two 128-Pin and One 160-pin (82344) Quad Flatpacks 1.0- and 1.5-
Micron CMOS
o Memory Control of One to Four Banks of 32-Bit DRAM Using 256K,
1M, or 4M Components Allowing 64 Mbytes on System Board
o Page Mode DRAM Operation on Any Number of Banks
o Two/Four-way Interleaving or Direct Access on System Board
Memory
o Programmable Option for Block or Word Interleave
o Programmable DRAM Timing Parameters
o Remap Option Allows Logical Reordering of System Board DRAM
o System Board Refresh Optionally Decoupled from Slot Bus
Refresh
o Staggered Refresh Minimizes Power Supply Load Variations
o Built-in "Sleep" Mode Features Including Use of Slow Refresh
DRAMs in Power Critical Operations
o EMS Hardware Supports Full LIM EMS 4.0 Spec over Entire 64 Mbyte
o DMA Expanded to Allow Transfer over 64M range
o Support for 387DX Numerical Coprocessors
o Coprocessor Software Reset can be Disabled
o Internal Switching and Programmable CLK2 Support for Slow and
"Turbo" Modes
o Programmable Drive Reduces the Need for External Buffering on DRAM
and Slot Bus Interface Signals Allows
o ISA Bus Control of 386 DX-Based PC/AT-Compatibles. Capable of
Asynchronous or Synchronous Bus Operation to 16 MHz
o Compatible with Lotus 1-2-3 Version 3.0 in 1M Systems
o Bus "Quiet" Mode Assures that Slot Bus Signal Lines are Driven Only
During Slot Accesses
o Integrated Peripheral Functions:
- Two 82C37A DMA Controllers with Extended 74LS612 Page Register
- Two 82C59A Interrupt Controllers
- One 82C54 Timer
- One 148618 Real Time Clock
o Additional 64 Bytes of Battery Backed RAM in RTC Provides for Non-
Volatile Storage of 82340DX Chip Set Configuration Data and User
Specific Information
o Supports 8- or 16-Bit Wide BIOS ROMs
o Cache Support for Posted Writes
o System Memory on MD or D Bus in Non-Cached Systems
o Separate Parity Generators/Checkers for High Speed Operation
o Internal I/O Programmable for 10- or 16-Bit Decode
o Three-State Control Pins Added for Board Level Testability
**82340SX Chip Set (VLSI) (82343/82344) 01/25/89...
**82350 EISA Chip Set 07/10/89...
**82350DT EISA Chip Set 04/22/91
***Notes:
date source: TimelineDateSort7_05.pdf
Information taken from: Intel_Peripheral_Components_1994.pdf*
1992-Oct_82351.pdf
1991-Oct_82353.pdf
1992-Oct_82352DT.pdf
1994-May_82355.pdf
1992-Oct_82357.pdf, 1994-Mar_82357.pdf
1991-Oct_82358DT.pdf
1992-Oct_82359.pdf
>*Section:
"General / 82350 EISA Chip Set" ----------------- dated Sep 1992
"82351 Local I/O EISA Support Peripheral (LIO.E)" dated Oct 1992
"82352DT EISA Bus Buffer (EBB)" ----------------- dated Oct 1993
"82357 Integrated System Peripheral (ISP)" ------ dated Oct 1992
"82358DT EISA Bus Controller" ------------------- dated Oct 1992
"82355 Bus Master Interface Controller (BMIC)" -- dated Sep 1993
All information is taken from the above source, unless stated
otherwise below:
#1 Information taken from: 1992-Oct_82359.pdf, for section "82359 DRAM
Controller" is solely from this source.
#2 Information taken from: 1994-May_82355.pdf, is identical to that in
the first reference.
#3 Information taken from: 1991-Oct_82358DT.pdf, contains the
additional feature:
• [Supports i486 Burst Cycles to the EISA/ISA Bus When Configured
for 82350DT Systems]
In the Info section, all text after "2.0 INTRODUCTION" is solely
from this source.
#4 Information taken from: 1992-Oct_82357.pdf, is identical in the
feature section. In the Info section, all text is solely from
this source. Of the quoted text the 1994-Mar_82357.pdf is the same.
#5 Information taken from: 1992-Oct_82352DT.pdf, contains some
differences in the feature section. This earlier source has the
following feature:
• The 82352 Interfaces Easily to the System...
instead of:
• The 82352DT Interfaces Easily to the System...
Also it contains the two additional features:
• The 82352 and 82352DT are Socket Compatible
• The 82352DT is Designed to Meet All of the 82352 Specifications
The quoted text in the info section is the same. This source
provides further detailed information.
#6 Information taken from: 1992-Oct_82351.pdf, is identical in the
feature section. In the Info section, all text is solely from
this source.
#7 Information taken from: 1991-Oct_82353.pdf, for section "82353
Advanced Data Path Device" is solely from this source.
The code name for this chipset is "Mongoose" see:
Computerworld Apr 15, 1991 p106 - Back on the Bus
***Info:...
***Configurations:...
***Features:...
**82420TX/ZX PCIset (for 486) TX (Saturn), ZX (Saturn II) c:Nov92...
**82420EX PCIset (for 486) EX (Aries) (82425EX/82426EX) <Dec94...
**82430LX PCIset (Pentium) LX (Mercury) (82433LX/82434LX) 03/22/93...
**82430NX PCIset (Pentium) NX (Neptune) (82433NX/82434NX) Mar94...
**82430FX PCIset (Pentium) FX (Triton I) (82437FX/82438FX)01/31/95...
**82430MX PCIset (Pentium) MX (Mobile Triton)(82437/438MX)11/01/95...
**82430HX PCIset (Pentium) HX (Triton II) (82439HX) 02/12/96...
**82430VX PCIset (Pentium) VX (Triton II) (82437VX/82438) 02/12/96...
**82430TX PCIset (Pentium) TX (Triton II) (82439TX) 02/17/97...
**82450KX/GX PCIset (Pentium Pro) KX/GX (Mars/Orion) 11/01/95...
**
**Support Chips:
**82091AA Advanced Interface Peripheral (AIP) c93...
**8289 Bus Arbiter (808x) c79...
**82289 Bus Arbiter for iAPX 286 Processor Family c83...
**82258 Advanced Direct Memory Access Coprocessor(ADMA) 01/01/84...
**82335 High-Integration Interface Device For 386SX c:Nov88...
**82360SL I/O Subsystem 10/05/90...
**82370 Integrated System Peripheral (for 82376) c:Oct88...
**82371FB/SB PCI ISA IDE Xcelerator 82371FB/82371SB (PIIX/3) 01/31/95...
**82371MX Mobile PCI I/O IDE Xcelerator (MPIIX) 11/01/95...
**82371AB PCI-TO-ISA / IDE Xcelerator 82371AB (PIIX4) 02/17/97...
**82374/82375 PCI-EISA Bridge (82374EB/82375EB, 374SB/375SB) c:Mar93...
**82378 System I/O (SIO) (82378IB and 82378ZB) c:Mar93...
**82379AB System I/O-APIC (SIO.A) <Dec94...
**82380 32-bit DMA Controller w/ Integrated Peripherals 02/01/87...
**82380FB/AB PCIset: 82380FB Mobile PCI-to-PCI Bridge(MPCI2) 02/17/97...
**82384 Clock Generator and Reset Interface c86...
**82385 32-bit Cache Controller for 80386 09/29/87...
**82385SX 32-bit Cache Controller for 80386SX 01/25/89...
**82395DX High Performance Smart Cache 06/18/90...
**82395SX Smart Cache 12/17/90...
**82396SX Smart Cache 12/17/90...
**82485 Turbo Cache (and 485Turbocache) c90...
**82489DX Advanced Programmable Interrupt Controller 10/12/92...
**82495DX/490DX DX CPU-Cache Chip Set <Sep91...
**82495XP/490XP Cache Controller / Cache RAM (for i860) 06/05/91...
**82496/491 Cache Controller / Cache RAM (for P5 Pentium) 03/22/93...
**82497/492 Cache Controller / Cache RAM (for P54 Pentium) <Nov94...
**82498/493 Cache Controller / Cache RAM (for P54 Pentium) <Nov94...
**
**Later chipsets (basic spec):
**440 series:
***440FX (Natoma) 05/06/96...
***440LX (Balboa) 08/27/97...
***440BX (Seattle) c:Apr'98...
***440DX (?) c:?...
***440EX (?) c:Apr'98...
***440GX (Marlinespike) 06/29/98...
***440ZX & 440ZX-66 (?) 01/04/99...
***440ZX-M (?) 05/17/99...
***440MX (Banister) 05/17/99...
**450NX (?) 06/29/98:...
**????? (Profusion) c:99...
**800 series...
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