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**Definition of a chip set:
In short it is a set of  chips that allow a system designer to build a
computer.  If we restrict the term  'chip' to that of a microchip then
technically any microcomputer  contains a chip set, even  one based of
7400-series logic alone.

In the context of this document, a chip set is defined as any group of
chips used to implement  an IBM or IBM-compatible PC/XT/AT/386/486/etc
system.

There are 2 main categories that these chips fall into:
1. Direct copies or re-implementations of Intel chips
2. Chip sets sold as a set of chips to implement an IBM-compatible 
   that differ in some way to those used in an IBM system, e.g. not 
   pin compatible.

An  example of  the former  would be  some early  chips built  by VLSI
Technology (at the time known as VTI, to implement a 286:
o  VL82C37A is a: 82C37A DMA controller
o  VL82C59A is a: 82C59A interrupt controller
o  VL82C54A is a: 82C54 timer
o  VL82C612 is a: 74LS612 memory mapper
o  VL82C84A is a: 82284 clock generator and ready interface
o  VL82C88  is a: 82288 bus controller

These are  all direct replacements  for the parts  used in an  IBM AT.
Many companies had compatible versions of these chips.

An early example of the latter is the Chips & Technology NEAT chip set:
o  82C211 CPU/Bus controller, 
o  82C212 Page/Interleave and EMS Memory controller, 
o  82C215 Data/Address buffer 
o  82C206 Integrated Peripherals Controller (IPC).

The description does not map directly to the parts used in the IBM AT.
Later chip sets are often even more integrated sometimes consisting of
just one chip, although two seems to be the most common.

The latter  is generally considered  the definition of a  chip set, and
the former is not generally  considered a chip set per-se. However when
looking  at   the  early  chip sets   this  distinction  can   be  very
slight. Because of this,  sets of chips  meeting the criteria  for (1.)
have been included where possible. 

**'chip set', 'chip-set' or 'chipset'?...
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**A note on VESA support of 486 chipsets....
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**82497/492   Cache Controller / Cache RAM (for P54 Pentium)    <Nov94
***Notes:...
***Info:...
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***Features:...
**82498/493   Cache Controller / Cache RAM (for P54 Pentium)    <Nov94...
**
**Later chipsets (basic spec):
**440 series:...
**450NX  (?)            06/29/98:...
**?????  (Profusion)    c:99...
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**SL82C365    Cache Controller (for 386DX/SX)                     c:91
***Info:
The SL82C365 supports direct-mapped cache system with data size ranged
from  16KB to  1MB  and line  size  ranged from  1  to 4  doublewords.
Without any  external logic, SL82C365 supports  1 to 4  banks of cache
SRAMs  independent of  the  line  size.  An  8-bit  tag comparator  is
integrated into the  chip which not only saves on  the system cost but
also improves  the overall performance.   25ns tag SRAM and  35ns data
SRAM   are  adequate   for   zero  wait   state  non-pipelined   33Mhz
operation. Assuming  8Kx8, 16Kx4, 32Kx8  and 64Kx4 SRAMs are  used for
tag SRAM, the selectable organization  is indicated in Table 1-1. [see
datasheet]  More options  are  available for  data RAM  configurations
because of the flexibility in  selecting the number of banks. Refer to
section 1.13 [see datasheet] for detailed design examples.

***Versions:...
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**SL82C465    Cache Controller (for 486/386DX/SX)                 c:91...
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