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**Definition of a chip set:
In short it is a set of  chips that allow a system designer to build a
computer.  If we restrict the term  'chip' to that of a microchip then
technically any microcomputer  contains a chip set, even  one based of
7400-series logic alone.

In the context of this document, a chip set is defined as any group of
chips used to implement  an IBM or IBM-compatible PC/XT/AT/386/486/etc
system.

There are 2 main categories that these chips fall into:
1. Direct copies or re-implementations of Intel chips
2. Chip sets sold as a set of chips to implement an IBM-compatible 
   that differ in some way to those used in an IBM system, e.g. not 
   pin compatible.

An  example of  the former  would be  some early  chips built  by VLSI
Technology (at the time known as VTI, to implement a 286:
o  VL82C37A is a: 82C37A DMA controller
o  VL82C59A is a: 82C59A interrupt controller
o  VL82C54A is a: 82C54 timer
o  VL82C612 is a: 74LS612 memory mapper
o  VL82C84A is a: 82284 clock generator and ready interface
o  VL82C88  is a: 82288 bus controller

These are  all direct replacements  for the parts  used in an  IBM AT.
Many companies had compatible versions of these chips.

An early example of the latter is the Chips & Technology NEAT chip set:
o  82C211 CPU/Bus controller, 
o  82C212 Page/Interleave and EMS Memory controller, 
o  82C215 Data/Address buffer 
o  82C206 Integrated Peripherals Controller (IPC).

The description does not map directly to the parts used in the IBM AT.
Later chip sets are often even more integrated sometimes consisting of
just one chip, although two seems to be the most common.

The latter  is generally considered  the definition of a  chip set, and
the former is not generally  considered a chip set per-se. However when
looking  at   the  early  chip sets   this  distinction  can   be  very
slight. Because of this,  sets of chips  meeting the criteria  for (1.)
have been included where possible. 

**'chip set', 'chip-set' or 'chipset'?...
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**Who made the first chip set?...
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**A note on VESA support of 486 chipsets....
**Datasheets:...
*_IBM...
*ACC Micro...
*ALD...
*ALi...
*AMD . . . . . . . [no datasheets, some info]...
*Chips & Technologies...
*Contaq  . . . . . [no datasheets, some info]...
*Efar Microsystems [no datasheets, some info]...
*ETEQ...
*Faraday...
*Forex . . . . . . [List only, no datasheets found]...
*Intel...
**82495XP/490XP Cache Controller / Cache RAM (for i860)       06/05/91
***Notes:...
***Info:
The Intel 82495XP cache controller and 82490XP cache RAM, when coupled
with a user-implemented memory  bus controller, provide a second-level
cache  subsystem  that eliminates  the  memory  latency and  bandwidth
bottleneck for  a wide  range of multiprocessor  systems based  on the
i860 XP  microprocessor. The CPU  interface is optimized to  serve the
i860  XP microprocessor  with zero  wait  states at  up to  50 MHz.  A
secondary cache  built from the  82495XP and 82490XP isolates  the CPU
from  the memory subsystem;  the memory  can run  slower and  follow a
different protocol than the i860 XP microprocessor.
         
***Features:...
**82496/491     Cache Controller / Cache RAM (for P5 Pentium) 03/22/93...
**82497/492   Cache Controller / Cache RAM (for P54 Pentium)    <Nov94...
**82498/493   Cache Controller / Cache RAM (for P54 Pentium)    <Nov94...
**
**Later chipsets (basic spec):
**440 series:...
**450NX  (?)            06/29/98:
Chips:
[82454NX] (PXB) [82453NX] (MUX) 
[82452NX] (RCG) [82451NX] (MIOC) 
[82371EB] (PIIX4E),                            
CPUs:          Single/Dual/Quad P-II Xeon/P-III Xeon
DRAM Types:    FPM EDO 2-way Interleave 4-way Interleave
Mem Rows:      8
DRAM Density:  16Mbit 64Mbit
Max Mem:       8GB
ECC/Parity:    Both
AGP speed:     N/A
Bus Speed:     100
PCI Clock/Bus: 1/3


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