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**82340DX Chip Set (VLSI) (82346/82345/82355) 01/08/90
***Notes:...
***Info:
****82346 System Controller:...
****82345 Data Buffer:
The 82345 Data Buffer is part of a custom, three chip set which allows
extremely high performance and integration in 386 DX processor based
PC/AT-compatible, personal computer designs. When used with the 82346
System Controller and the 82344 ISA Bus Controller, the set is called
the 82340DX chip set.
The 82345 performs all the data buffering functions required for a 386
DX-based PC/AR-type system. Under the control of the CPU, the data
buffer chip routes data to and from the CPU bus, the MD bus, the XD
bus, and the slots (SD bus). For an on-board DRAM read, the data is
latched in the MD latch allowing the 82346 System Controller to be
programmed for early CAS terminations. The parity is checked for MD
bus read operations and any errors are reported during the next read
cycle. When reading from ROM, the XD bus or the SD bus, the data can
be converted from 8-bits wide to 16-, 24- or 32-bits wide or from 16
bits to 32 bits at the 16/32 latch. the data is latched with LATLO#
and LATHI# for synchronization with the CPU. The data conversion is
accomplished without the use of the bus size 16 (BS16#) input to the
386DX allowing it to remain in pipelined mode.
CPU writes to any of the three buses are accomplished in several
different ways. The 82345 supports posted writes from a cache
controller or non-posted writes to the MD bus. Parity is generated for
all data written to the MD bus. The 82345 provides the data
conversion necessary for 32- or 16-bit writes to 16- or 8-bit devices
on the XD or SD bus.
In non-cached systems, system board DRAM can be placed on either the
MD bus or the CPU's D bus. In slower systems ( \< 16 MHz) true zero
wait state operation is possible with available 60 ns DRAMs when the D
bus is used. This is due to the extra timing margin available when the
MD bus delay through the 82345 is removed from the critical path.
Faster non-cached systems can come close to zero wait state
performance using 80 ns to 100 ns DRAMs and page mode inter-
leaving. This requires an even number of DRAM banks.
Under the control of DMA or a bus master, the 82345 will allow 8- or
16-bit data to be routed to and from the XD and the MD buses. The chip
also is capable of performing high to low and low to high byte swaps
on the SD bus. For transfers between two peripherals on the slot bus,
the outputs of the 82345 will be disabled. The chip also provides the
feature of a single input, TRI#, to disable all of its outputs for
board level testability.
****82344 ISA Bus Controller:...
***Configurations:...
***Features:...
**82340SX Chip Set (VLSI) (82343/82344) 01/25/89...
**82350 EISA Chip Set 07/10/89...
**82350DT EISA Chip Set 04/22/91...
**82420TX/ZX PCIset (for 486) TX (Saturn), ZX (Saturn II) c:Nov92...
**82420EX PCIset (for 486) EX (Aries) (82425EX/82426EX) <Dec94...
**82430LX PCIset (Pentium) LX (Mercury) (82433LX/82434LX) 03/22/93...
**82430NX PCIset (Pentium) NX (Neptune) (82433NX/82434NX) Mar94...
**82430FX PCIset (Pentium) FX (Triton I) (82437FX/82438FX)01/31/95...
**82430MX PCIset (Pentium) MX (Mobile Triton)(82437/438MX)11/01/95...
**82430HX PCIset (Pentium) HX (Triton II) (82439HX) 02/12/96...
**82430VX PCIset (Pentium) VX (Triton II) (82437VX/82438) 02/12/96...
**82430TX PCIset (Pentium) TX (Triton II) (82439TX) 02/17/97...
**82450KX/GX PCIset (Pentium Pro) KX/GX (Mars/Orion) 11/01/95...
**
**Support Chips:
**82091AA Advanced Interface Peripheral (AIP) c93...
**8289 Bus Arbiter (808x) c79...
**82289 Bus Arbiter for iAPX 286 Processor Family c83...
**82258 Advanced Direct Memory Access Coprocessor(ADMA) 01/01/84...
**82335 High-Integration Interface Device For 386SX c:Nov88...
**82360SL I/O Subsystem 10/05/90...
**82370 Integrated System Peripheral (for 82376) c:Oct88...
**82371FB/SB PCI ISA IDE Xcelerator 82371FB/82371SB (PIIX/3) 01/31/95...
**82371MX Mobile PCI I/O IDE Xcelerator (MPIIX) 11/01/95...
**82371AB PCI-TO-ISA / IDE Xcelerator 82371AB (PIIX4) 02/17/97...
**82374/82375 PCI-EISA Bridge (82374EB/82375EB, 374SB/375SB) c:Mar93...
**82378 System I/O (SIO) (82378IB and 82378ZB) c:Mar93...
**82379AB System I/O-APIC (SIO.A) <Dec94...
**82380 32-bit DMA Controller w/ Integrated Peripherals 02/01/87...
**82380FB/AB PCIset: 82380FB Mobile PCI-to-PCI Bridge(MPCI2) 02/17/97...
**82384 Clock Generator and Reset Interface c86...
**82385 32-bit Cache Controller for 80386 09/29/87...
**82385SX 32-bit Cache Controller for 80386SX 01/25/89...
**82395DX High Performance Smart Cache 06/18/90...
**82395SX Smart Cache 12/17/90...
**82396SX Smart Cache 12/17/90...
**82485 Turbo Cache (and 485Turbocache) c90...
**82489DX Advanced Programmable Interrupt Controller 10/12/92...
**82495DX/490DX DX CPU-Cache Chip Set <Sep91...
**82495XP/490XP Cache Controller / Cache RAM (for i860) 06/05/91...
**82496/491 Cache Controller / Cache RAM (for P5 Pentium) 03/22/93...
**82497/492 Cache Controller / Cache RAM (for P54 Pentium) <Nov94...
**82498/493 Cache Controller / Cache RAM (for P54 Pentium) <Nov94...
**
**Later chipsets (basic spec):
**440 series:
***440FX (Natoma) 05/06/96...
***440LX (Balboa) 08/27/97...
***440BX (Seattle) c:Apr'98...
***440DX (?) c:?...
***440EX (?) c:Apr'98...
***440GX (Marlinespike) 06/29/98...
***440ZX & 440ZX-66 (?) 01/04/99...
***440ZX-M (?) 05/17/99...
***440MX (Banister) 05/17/99...
**450NX (?) 06/29/98:...
**????? (Profusion) c:99...
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