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**SL9011   System Controller (80286/80386SX/DX, 16/20/25MHz)    <Jan90
***Info:...
***Versions:...
***Features:...
**SL9020   Data Controller                                      <Jan90...
**SL9025   Address Controller                                   <Jan90...
**SL9030   Integrated Peripheral Controller                     <Jan90...
**SL9090/A Universal PC/AT Clock Chip                           <oct88
***Info:...
***Versions:...
***Features:...
**SL9095   Power  Management Unit                                    ?...
**SL9151   80286 Page Interleave Memory Controller (16-25MHz)        ?...
**SL9250   80386SX Page Mode Memory Controller (16/20MHz 8MB)        ?...
**SL9251   80386SX Page Interleave Memory Controller         <04/13/90...
**SL9252   80386SX System and Memory Controller              <06/12/90...
**SL9350   80386DX Page Mode Memory Controller (16-25MHz 16MB)       ?...
**SL9351   80386DX Page Interleave Memory Controller (33MHz)         ?...
**SL9352   80386DX System and Memory Controller              <06/12/90...
**SLXXXX   Other chips...
**
**VT82C470     "Jupiter", Chip Set (w/o cache) 386 [no datasheet]    ?
**VT82C475     "Jupiter", Chip Set (w/cache) 386   [no datasheet]    ?
**VT82C486/2/3 "GMC chipset"            [no datasheet, some info]    ?
***Notes:...
***Info:
8) The VIA GMC chipset  (VIA:  1106/4358) (5/18/96)
  --------------------

This  chipset  includes  the  VIA VT82C486A-F  with  a  built-in  8042
keyboard controller and  a VIA VT82C505-D chipset for the  VESA to PCI
bridge.  Specifically, the chips are as follows:

82C486A - cache/memory controller + VLB to ISA bridge
82C482 - VLB to ISA bridge (why there are two I'm not sure)
82C483 - DRAM controller
VT82C505 PCI to VLB bridge

A board using this chipset has been unstable (even under DOS/Win), and
did not work  with an Adaptec 2940 SCSI controller  under OS/2 at all.
Boards based  on this chipset  are therefore  to be avoided.   I have,
however, had  one report of success  from someone using revision  G of
this chipset, so it could be that the new revision fixes problems with
older  rev's.  Designers  with  whom I've  corresponded indicate  that
improperly designed  boards which use  this chipset may  have unstable
caches.  In  addition, the  cache controller reads  the data  into the
cache SRAMs first, then into  the CPU, increasing latency and reducing
throughput.

***Configurations:...
**VT82C495/480 "Venus" Chip Set                    [no datasheet]    ?
**VT82C495/491 ? EISA Chip Set          [no datasheet, some info]  <93...
**VT82C496G    Pluto, Green PC 80486 PCI/VL/ISA System       <05/30/94...
**VT82C530MV   3.3V Pentium chipset [no datasheet, some info]<05/30/94...
**VT82C570M    Apollo Master, Green Pentium/P54C             <06/22/95...
**VT82C580VP   Apollo VP,  Pentium/M1/K5 PCI/ISA System      <02/15/96...
**VT82C580VPX  Apollo VPX, VPX/97, Pentium with 66/75MHz Bus <01/09/97...
**VT82C590     Apollo VP2, VP2/97, Single-Chip Pentium 66MHz <01/10/97...
**VT82C597/AT  Apollo VP3, Single-Chip for Pentium with AGP  <10/03/97...
**VT82C598MVP  Apollo MVP3,Single-Chip 66/75/83/100MHz & AGP <09/22/97...
**VT8501       Apollo MVP4,Single-Chip 66-100MHz & AGP       <11/04/98...
**VT82C680     Apollo P6, Pentium-Pro Chip Set               <08/30/96...
**Support chips:
**VT82C505     Pentium/486 VL to PCI Bridge                  <05/30/94...
**VT82C586/A/B PCI Integrated Peripheral Controller          <10/13/96...
**VT82C596/A   Mobile PCI Integrated Peripheral Controller   <11/05/97...
**VT82C686A/B  PCI Super-I/O Integrated Peripheral Ctrl.     <02/10/98...
**Later P-Pro/II/III/Celeron...
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