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**ACC2268 ?486 [no datasheet] ?
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**ACC???? Maple/Maple-133 486-System-On-Chip [no datasheet] ?...
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**ACC2016 Buffer and MUX Logic c96...
**ACC2020 Power Management Chip c92...
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**82384 Clock Generator and Reset Interface c86
***Notes:...
***Info:
The M82384 combines a third-overtone crystal oscillator, reset
synchronizing circuitry, and address status circuitry onto a single
chip for easy timing and control of Military 386 microprocessor-based
systems.
The M82384 contains a clock generator/driver that provides two clock
signals for the Military microprocessor-based systems. The CLK2 signal
generated by the M82384 meets the Military 386 processor CLK2
requirements, and the CLK signal indicates the Military 386 processor
phase. The M82384 also generates a synchronous reset signal from a
schmitt-trigger reset input, and provides an Address Status signal
that has guaranteed setup and hold timing with respect to the CLK
output.
***Versions:...
***Features:...
**82385 32-bit Cache Controller for 80386 09/29/87...
**82385SX 32-bit Cache Controller for 80386SX 01/25/89...
**82395DX High Performance Smart Cache 06/18/90...
**82395SX Smart Cache 12/17/90...
**82396SX Smart Cache 12/17/90...
**82485 Turbo Cache (and 485Turbocache) c90...
**82489DX Advanced Programmable Interrupt Controller 10/12/92...
**82495DX/490DX DX CPU-Cache Chip Set <Sep91...
**82495XP/490XP Cache Controller / Cache RAM (for i860) 06/05/91...
**82496/491 Cache Controller / Cache RAM (for P5 Pentium) 03/22/93...
**82497/492 Cache Controller / Cache RAM (for P54 Pentium) <Nov94...
**82498/493 Cache Controller / Cache RAM (for P54 Pentium) <Nov94...
**
**Later chipsets (basic spec):
**440 series:...
**450NX (?) 06/29/98:
Chips:
[82454NX] (PXB) [82453NX] (MUX)
[82452NX] (RCG) [82451NX] (MIOC)
[82371EB] (PIIX4E),
CPUs: Single/Dual/Quad P-II Xeon/P-III Xeon
DRAM Types: FPM EDO 2-way Interleave 4-way Interleave
Mem Rows: 8
DRAM Density: 16Mbit 64Mbit
Max Mem: 8GB
ECC/Parity: Both
AGP speed: N/A
Bus Speed: 100
PCI Clock/Bus: 1/3
**????? (Profusion) c:99...
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