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**82396SX     Smart Cache                                     12/17/90
***Notes:...
***Info:...
***Versions:...
***Features:
o   Optimized Intel386TM SX Microprocessor Companion
o   4 Way SET Associative with Pseudo LRU Algorithm
o   Write Buffer Architecture
o   Integrated 4 Word Write Buffer
o   Integrated Intel387TM SX Math Coprocessor Decode Logic
o   132 Lead PQFP Package
o   Intel486TM SX Microprocessor like Burst
o   Integrated 16 KB Data RAM 
o   16-Byte Line Size
o   Dual Bus Architecture
    - Snooping Maintains Cache Coherency
o   20 MHz Clock
o   Concurrent Line Buffer Cacheing
o   1K of TAG RAM
o   Non-Sectored Architecture

**82485       Turbo Cache (and 485Turbocache)                      c90...
**82489DX       Advanced Programmable Interrupt Controller    10/12/92...
**82495DX/490DX DX CPU-Cache Chip Set                           <Sep91...
**82495XP/490XP Cache Controller / Cache RAM (for i860)       06/05/91...
**82496/491     Cache Controller / Cache RAM (for P5 Pentium) 03/22/93...
**82497/492   Cache Controller / Cache RAM (for P54 Pentium)    <Nov94...
**82498/493   Cache Controller / Cache RAM (for P54 Pentium)    <Nov94...
**
**Later chipsets (basic spec):
**440 series:...
**450NX  (?)            06/29/98:...
**?????  (Profusion)    c:99
Chips:         
Memory Access Controller (MAC)  
Data Interface Buffer (DIB)
CPUs:          8x P-III Xeon Oct
DRAM Types:    SDRAM PC100 2-way Interleave dual channel
Max Mem:       32GB
ECC/Parity:    ECC
AGP speed:     N/A
Bus Speed:     100
PCI Clock/Bus: 1/3 PCI-66/64



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