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**EFAR-8290WB 386/486 Writeback PC/AT Chipset     [no datasheet]     ?
***Notes:...
***Info:
82EC495 System Controller (SYSC)

SYSC  monitors two  reset  sources, RSTl##  and  RST2#, and  generates
CPURST and  NPRST signals to  CPU and coprocessor,  respectively.  The
SYSC Controller contains Burst Line Fill Control Logic. The controller
provides 2 DMA Upper Address Latches, Page Mode DRAM Controller, Clock
Generation  for CPU  Processor  and AT-Bus,  two Noncacheable  Address
Comparators,  CPU  Interface   Control,  Integrated  Write-back  Cache
Controller with Built-in Tag  Comparator, Decoupling Refresh for Local
DRAM and AT-Bus Memory.

82EC392 Data Buffer Controller (DBC)

The 82EC392  performs all of  the data buffering functions.  Under the
control  of the processor,  the 82EC392  routes data  to and  form the
local CPU Bus.

The DBC performs Data Bus Conversion  when CPU accesses to 16 or 8 bit
device  through 32/16  bit instruction.   The bus  conversion  is also
supported for DMA/Master cycle for  the transfer between local DRAM or
cache memory and devices which resides on AT bus.

Parity Generation/Detection Logic will  compare the parity bit and the
parity generated from the data byte. If a mismatch happens, the parity
error will be generated.

In  order to  reduce  the  components count,  DBC  provides the  clock
sources for the timer of 8OC206 and 8042 Keyboard Controller.

The DBC  also monitors both  the PWGDS# (Powergood) signal  from power
supply and reset  signal from the reset switch.   The DBC provides the
Numeric Coprocessor  support for 387 and 3167  without external logic
components.

In addition, the DBC provides  Chip Select for Keyboard Controller and
RTC, Keyboard Reset and  Gate A20Emulation Logic, Speaker Control, and
NMI Logic.

***Configurations:...
**82EC798     386/486 Writeback PC/AT Single Chip [no datasheet]     ?
**Other:...
*ETEQ...
*Faraday...
*Forex . . . . . . [List only, no datasheets found]...
*Intel...
**?????  (Profusion)    c:99
Chips:         
Memory Access Controller (MAC)  
Data Interface Buffer (DIB)
CPUs:          8x P-III Xeon Oct
DRAM Types:    SDRAM PC100 2-way Interleave dual channel
Max Mem:       32GB
ECC/Parity:    ECC
AGP speed:     N/A
Bus Speed:     100
PCI Clock/Bus: 1/3 PCI-66/64



**800 series...
*Headland/G2...
*HMC (Hulon Microelectronics)...
*Logicstar...
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*OPTi...
**82C700         FireStar                                         c:97
***Info:...
***Configurations:...
***Features:...
**82C701         FireStar Plus                                    c:97...
**82C750         Vendetta      [no datasheet]                        ?...
**82c801         SCWB2 DX Single Chip Solution                    c:92...
**82C802         SCWB2 PC/AT Single Chip [no datasheet]              ?...
**82C802G/GP     System/Power Management Controller (cached)      c:93...
**82C895         System/Power Management Controller (cached)   c:Sep94...
**82C898         System/Power Management Controller (non-cache)c:Nov94...
**
**Support Chips:
**82C601/2       Buffer Devices                                 <Nov94...
**82C822         PCIB (VLB-to-PCI bridge)                         c:94...
**Other:...
*PC CHIPS/Amptron/Atrend/ECS/Elpina/etc...
*SIS...
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*TI (Texas Instruments)...
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*Unresearched:...
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