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**Spelling errors/mistyped words
Yes, I  know there are  spelling errors,  and things are  mistyped. It
seems no matter  how hard I try  my fingers hit 't'  twice when typing
'compatible' rendering it 'compattible' numerous, (thousands actually)
times.  I  don't have the  time or the will  to check the  spelling of
everything. Basic spell checking has been peformed. Please let me know
if  there is  anything that  would lead  to incorrect  information, or
something  is so  mangled  that  it needs  revising.  But  if you  can
basically  understand  what was  intended,  just  cope with  it.  Just
cope:-)

BTW, "110" port is  an "I/O" port that has been OCRed  badly, as is an
"1/0" port.

**Info needed on:...
**A note on VESA support of 486 chipsets....
**Datasheets:...
*_IBM...
*ACC Micro...
*ALD...
*ALi...
*AMD . . . . . . . [no datasheets, some info]...
*Chips & Technologies...
*Contaq  . . . . . [no datasheets, some info]...
*Efar Microsystems [no datasheets, some info]...
**EFAR-8290WB 386/486 Writeback PC/AT Chipset     [no datasheet]     ?
***Notes:...
***Info:
82EC495 System Controller (SYSC)

SYSC  monitors two  reset  sources, RSTl##  and  RST2#, and  generates
CPURST and  NPRST signals to  CPU and coprocessor,  respectively.  The
SYSC Controller contains Burst Line Fill Control Logic. The controller
provides 2 DMA Upper Address Latches, Page Mode DRAM Controller, Clock
Generation  for CPU  Processor  and AT-Bus,  two Noncacheable  Address
Comparators,  CPU  Interface   Control,  Integrated  Write-back  Cache
Controller with Built-in Tag  Comparator, Decoupling Refresh for Local
DRAM and AT-Bus Memory.

82EC392 Data Buffer Controller (DBC)

The 82EC392  performs all of  the data buffering functions.  Under the
control  of the processor,  the 82EC392  routes data  to and  form the
local CPU Bus.

The DBC performs Data Bus Conversion  when CPU accesses to 16 or 8 bit
device  through 32/16  bit instruction.   The bus  conversion  is also
supported for DMA/Master cycle for  the transfer between local DRAM or
cache memory and devices which resides on AT bus.

Parity Generation/Detection Logic will  compare the parity bit and the
parity generated from the data byte. If a mismatch happens, the parity
error will be generated.

In  order to  reduce  the  components count,  DBC  provides the  clock
sources for the timer of 8OC206 and 8042 Keyboard Controller.

The DBC  also monitors both  the PWGDS# (Powergood) signal  from power
supply and reset  signal from the reset switch.   The DBC provides the
Numeric Coprocessor  support for 387 and 3167  without external logic
components.

In addition, the DBC provides  Chip Select for Keyboard Controller and
RTC, Keyboard Reset and  Gate A20Emulation Logic, Speaker Control, and
NMI Logic.

***Configurations:...
**82EC798     386/486 Writeback PC/AT Single Chip [no datasheet]     ?
**Other:...
*ETEQ...
*Faraday...
*Forex . . . . . . [List only, no datasheets found]...
*Intel...
**82496/491     Cache Controller / Cache RAM (for P5 Pentium) 03/22/93
***Notes:...
***Info:...
***Configurations:...
***Features:...
**82497/492   Cache Controller / Cache RAM (for P54 Pentium)    <Nov94...
**82498/493   Cache Controller / Cache RAM (for P54 Pentium)    <Nov94...
**
**Later chipsets (basic spec):
**440 series:...
**450NX  (?)            06/29/98:...
**?????  (Profusion)    c:99...
**800 series...
*Headland/G2...
*HMC (Hulon Microelectronics)...
*Logicstar...
*Motorola...
*OPTi...
*PC CHIPS/Amptron/Atrend/ECS/Elpina/etc...
*SIS...
*Symphony...
*TI (Texas Instruments)...
*UMC...
*Unresearched:...
*VIA...
*VLSI...
*Western Digital...
*Winbond...
*ZyMOS...
*General Sources:...