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*Contaq  . . . . . [no datasheets, some info]...
**??????    486 EISA chipset [no datasheet]                     <Feb93
PC Mag 23 Feb 1993 p124 - 
Advert for DX2 66MHz EISA system, with Contaq chipset.

**82C599    PCI-VLB Bridge [no datasheet, some info]                 ?

82C599 PCI-VLB Bridge referenced in:
http://web.mit.edu/netbsd/src/sys/dev/pci/pcidevs

from:
https://web.archive.org/web/20050313090427/http://www.os2forum.or.at/english/info/os2hardwareinfo/pci_chips.html

"The Contaq Chipset (Contaq: 1080/4224) (8/27/95)

The Contaq 82C599  is paired with one of  their 486VL chipsets (82C596
or  82C597) and  bridges directly  from the  486 CPU  to the  PCI bus.
Paraphrased from the Contaq spec.:

The  82C596 system  controller provides  the CPU  interface,  VESA bus
interface, ISA bus controller, etc. The 82C599 PCI controller provides
the bridge  between PCI master/slave  agent and the  ISA/VESA standard
expansion  bus; it arbitrates  all the  bus transactions  between host
CPU, PCI agent, VESA device, and ISA device.

(Which sounds to me like the PCI bus is attached to the VL bus, rather
than to the CPU, which will cause PCI performance degradation.)"

**82C693    PCI-ISA Bridge [no datasheet]                            ?...
*Efar Microsystems [no datasheets, some info]...
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*Forex . . . . . . [List only, no datasheets found]...
*Intel...
**82495DX/490DX DX CPU-Cache Chip Set                           <Sep91
***Notes:...
***Info:...
***Configurations:...
***Features:
o   50 MHz Intel486 DX CPU 
    - RISC Integer Core with Frequent Instructions Executing in One 
      Clock
    - 160 Mbyte/Sec Burst Bus
    - 41 Dhrystone MIPs
    - 11.5M Double Precision Whetstones/Sec.
    - On-Chip Cache and FPU
o   Highly Flexible
    - Supports 128 Kbyte and 256 Kbyte Configurations
    - Complete MESI Protocol Support
    - 32- or 64-Bit Memory Bus Width
    - Synchronous, Asynchronous, and Strobed Memory Bus Protocols
    - Variable Cache Line Sizes and Sectoring
    - Cache Data Parity Option
o   High Performance Second Level Cache
    - Two-Way Set Associative
    - Write-Back or Write Through Cache
    - Zero Wait State Cache Access
    - Concurrent CPU Bus, Memory Bus, and Internal Array Operation
o   Full Multiprocessing Support
    - Implements MESI Write-Back Cache Protocol
    - Low Bus Utilization
    - Automatically Maintains 1st Level Cache Consistency
    - Supports Read-for-Ownership, Write-Allocation, and Cache-to-
      Cache Transfers

**82495XP/490XP Cache Controller / Cache RAM (for i860)       06/05/91...
**82496/491     Cache Controller / Cache RAM (for P5 Pentium) 03/22/93...
**82497/492   Cache Controller / Cache RAM (for P54 Pentium)    <Nov94...
**82498/493   Cache Controller / Cache RAM (for P54 Pentium)    <Nov94...
**
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**450NX  (?)            06/29/98:...
**?????  (Profusion)    c:99...
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**950        LPC I/O                                         <07/16/99
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